MVME51005E Single Board Computer Installation and Use

The MVME51005E Single Board Computer Installation and Use provides the information you will need to install and configure your MVME51005E Single Board Computer. It provides specific preparation and installation information and data applicable to the board. The MVME51005E will hereafter be referred to as the MVME5100.

The MVME5100 is a high-performance VME single board computer featuring the PowerPlus II architecture with a choice of processors–either the MPC7410 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750.

As of the printing date of this manual, the MVME5100 is available in the configurations shown below. Note: all models of the MVME5100 are available with either VME Scanbe front panel or IEEE 1101 compatible front panel handles.

Overview of Contents

The following paragraphs briefly describe the contents of each chapter.

Chapter 1, Hardware Preparation and Installation, provides a description of the MVME5100 and its main integrated PMC and IPMC boards. The remainder of the chapter includes an explanation of the installation procedure, including preparation and jumper setting information.

Chapter 2, Operation, provides a description of the operational functions of the MVME5100 including tips on applying power, a description of the switch settings, the status indicators, I/O connectors, and system power up information.

Chapter 3, PPCBug Firmware, provides an explanation of the debugger firmware, PPCBug, on the MVME5100. The chapter includes an overview of the firmware, a section on how to use PPCBug, a listing of the initialization steps, a brief explanation of the two main configuration commands CNFG and ENV, and a description of the standard configuration parameters. A listing of the basic commands are also provided.

pter 4, Functional Description, provides a summary of the MVME5100 features, a block diagram, and a description of the major functional areas.Chapter 5, RAM500 Memory Expansion Module, provides a description of the RAM500 Memory Expansion Module, a list of features, a block diagram of the module, a table of memory size allocations, an installation procedure, and pinouts of the module’s top and bottom side connectors.Chapter 6, Pin Assignments, provides a listing of all connector and header pin assignments for the MVME5100.

Chapter 7, Programming the MVME5100, provides a description of the memory maps on the MVME5100 including tables of default processor memory maps, suggested CHRP memory maps and Hawk PPC register values for suggested memory maps. The remainder of the chapter provides some programming considerations.

Appendix A, Specifications, provides the standard specifications for the MVME5100, as well as some general information on cooling.

Appendix B, Troubleshooting, provides a brief explanation of the possible resolutions for basic error conditions.

Appendix C, Thermal Analysis, gives systems integrators the information necessary to conduct thermal evaluations of the board in their specific system configuration. Appe

ndix D, Related Documentation, provides a listing of related documentation for the MVME5100, including vendor documentation and industry related specifications.Comments and SuggestionsWe

welcome and appreciate your comments on our documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to us by filling out the following online form: http://www.emersonnetworkpowerembeddedcomputing.com/ > Contact Us > Online FormIn “Area of Interest” select “Technical Documentation”. Be sure to include the title, part number, and revision of the manual and tell us how you used it.Conventions Used in This ManualThe following typographical conventions are used in this document:boldis used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.italicis used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.courieris used for syst

em output (for example, screen displays, reports), examples, and system prompts.<Enter>, <Return> or <CR><CR>repres

ents the carriage return or Enter key.

Unpacking Instructions

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

NoteIf the shipping carton(s) is/are damaged upon receipt, request that the carrier's agent be present during the unpacking and inspection of the equipment.

Use ESD

Wrist Strap

Emerson strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system.Electronic components, such as disk drives, computer boards and memory modules, can be extremely sensitive to electrostatic discharge (ESD). After removing the component from its protective wrapper or from the system, place the component on a grounded, static-free, and adequately protected working surface. Do not slide the component over any surface. In the case of a Printed Circuit Board (PCB), place the board with the component side facing up.

If an ESD station is not available, you can avoid damage resulting from ESD by wearing an antistatic wrist strap (available locally) that is attached to an active electrical ground.Note A system chassis may not be a suitable grounding source if it is unplugged.

Hardware and Firmware InitializationThe debugger performs the hardware and firmware initialization process. This process occurs each time the MVME5100 is reset or powered up. The steps listed below are a high-level outline; be aware that not all of the detailed steps are listed.1.Sets MPU.MSR to known value.2.Invalidates the MP

U's data/instruction caches.3.Clears all segment registers of the MPU.4.Clears all block address translation registers of the MPU.5.Initializes the MPU-bus-to-PCI-bus bridge device.6.Initializes the PCI-bus-to-ISA-bus bridge device.7.Calculates the external bus clock speed of the MPU.8.Delays for 750 milliseconds.9.Determines the CPU base board type.10.Sizes the local read/write memory (that is, DR AM).11.Initializes the read/write memory controller. Sets base address of memory to 0x00000000.12.Retrieves the speed of read/write memory.13.Initializes the read/write memory controller with the speed of read/write memory.14.Retrieves the speed of read only memory  (thatis,Flash).15.Initializes the read only memory controller with the speed of read only memory.16.Enables the MPU's instruction cache. 17.Copies the MPU's exception

vector table from 0xFFF00000 to 0x00000000.18.Verifies MPU type.19.Enables the superscalar feature of the MPU (superscalar processor boards only).20.Verifies the extern

al bus clock speed of the MPU.21.Determines the debugger's console/host ports and initializes the PC16550A.22.Displays the debugger's copyright message.23.Displays

any hardware initialization errors thatmay have occurred.24.Checksums the debugger object and displays a warning message if the checksum failed to verify.

25.Displays the amount of local read/write memory found.

26.Verifies the configuration data that is resident in NVRAM and displays a warning message if the verification failed.

27.Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verificationfails.

28.Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data,and displays a warning message if the verification fails.29.Probes PCI bus for supported network devices.30.Probes PCI bus for supported mass storage devices.31.Initializes the memory/IO addresses for the supported PCI bus devices.32.Executes Self-Test, if so configured. (Default is no Self-Test).33.Extinguishes the board fail LED, if Self-Test passed and outputs any warning messages.

34.Executes boot program, if so configured. (Default is no boot.)35.Executes the debugger monitor (that is, issues the PPC6-Bug> prompt). 

System Memory Controller and PCI Host Bridge：

The on-board Hawk ASIC provides the bridge function between the processor’s bus and the PCI bus. It provides 32-bit addressing and 64-bit data; however, 64-bit addressing (dual address cycle)is not supported. The ASIC also supports various processor external bus frequencies up to100 MHz.

There are four programmable map decoders for each direction to provide flexible address mappings between the processor and the PCI bus. The ASIC also provides an Multi-Processor Interrupt Controller (MPIC) to handle various interrupt sources. They are: four MPIC timer interrupts, interrupts from all PCI devices and two software interrupts.

Memory ：

The following subsections describe various memory capabilities on the MVME5100 including Flash memory and ECC SDRAM memory.

Flash Memory：

The MVME5100 contains two banks of Flash memory. Bank B consists of two 32-pin devices which can be populated with 1MB of Flash memory (only 8-bit writes are supported for this bank). Refer to the application note following for more write-protect information on this product.

Bank A has 4 16-bit Smart Voltage FLASH SMT devices. With 32Mbit flash devices, the flash memory size is 16MB. Note that only 32-bit writes are supported for this bank of flash memory.Application Note: For Am29DL322C or Am29DL323C, 32Megabit (4M x 8-Bit/2M x 16-bit) CMOS 3.0 Volt-only Flash Memory.TheWrite Protect function provides a hardware method of protecting certain boot sectors. If the system asserts V IL (low signal) on the WP#/ACC pin, the device disables the program and erase capability, independently of whether those sectors were protected or unprotected using the method described in the Sector/Sector Block Protection and Unprotection of the AMD datasheet. The two outermost 8Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device.

The aforementioned implemented device (at the time of this printing is the only qualified Flash device used on this product) is a top-boot device, and as such, the write protected area is in the upper 16KB of each device. Since it uses 4 devices for the soldered Flash bank, the write protected region corresponds to the upper 64KB of the soldered Flash memory map. Thus the address range of $F4FF 0000 to F4FF FFFF is the write protected region when the J16 header is jumpered across pins 2 and 3.If PPCBug tries to write to those write-protected address areas whenpins 2-3 on J16 are set, the command will simply not finish (i.e., erase sector function stops at $F4FF 0000).