ADLINK DAQ/DAQE/PXI-220x acquisition card fully configured

ADLINK DAQ/DAQE/PXI-220x Series Acquisition Card Configuration and Calibration

In the fields of high-precision multi-channel data acquisition, automated testing, and process monitoring, ADLINK's DAQ/DAQE/PXI-220x series high-performance multifunctional data acquisition cards have become an ideal choice for engineers to build complex measurement and control systems due to their flexible channel configuration, rich trigger modes, efficient DMA transfer, and synchronization capabilities. This series covers three bus specifications: DAQ (PCI), DAQE (PCIe), and PXI, including models 2204 (12 bit/3MS/s), 2205 (16 bit/500kS/s), 2206 (16 bit/250kS/s), and 2208 (96 channel/12 bit/3MS/s, without dual DA and GPTC). This article will provide you with a complete technical guide from hardware configuration, analog input/output, timer/counter, triggering and synchronization, calibration, and software ecology dimensions, from selection to in-depth application.

Analog input: channel, gain and input mode

The 220x series supports mixed configurations of single ended (SE) and differential (DI) inputs, and the software can be set channel by channel. Among them, 2204/2205/2206 provides 64 SE or 32 DI channels, while 2208 extends to 96 SE or 48 DI channels. Each channel can independently choose bipolar (± 10V, ± 5V, ± 2.5V, ± 1.25V, etc.) or unipolar (0~10V, 0~5V, 0~2.5V, 0~1.25V), and the gain range varies by model: 2204/2208 supports up to 10 levels of gain (× 1~× 200), while 2205/2206 provides × 1, × 2, × 4, × 8.

Key performance indicators (excerpted from the manual):

System noise: 2205 has a typical value of only 0.95 LSB rms in the ± 10V range, while 2206 has a lower value of 0.8 LSB rms.

CMRR: In differential mode, the ± 5V range can reach 90dB (DC~60Hz), effectively suppressing power frequency interference.

Input impedance: 1G Ω//100pF when powered on, suitable for high impedance signal sources; Overvoltage protection up to ± 30V (power on) and ± 15V (power off).

Practical input signal connection:

Floating ground signal (such as thermocouple): using RSE (Reference Single End) mode, the board provides ground reference; In differential mode, a resistor (approximately 100 times the source impedance) needs to be added between AIL and AIGND to provide a bias circuit.

Grounding reference signal (such as non isolated output): NRSE (non reference single ended) mode is recommended, where the signal is locally grounded to AISENSE and the common mode rejection of the instrument amplifier is used to eliminate the ground potential difference; Differential mode can also be used to directly connect AIH/AIL.

The channel gain queue (up to 512/1024 words) allows users to freely arrange the scanning order, with each entry specifying the channel number, range, and input type. For example, if the queue is set to ch1 (± 10V), ch2 (± 2.5V DIFF), and ch0 (0-5V), the sampling order will cycle in this way, greatly simplifying the mixed acquisition of multiple types of signals.

Scanning acquisition and triggering mode: precise timing and event synchronization

To obtain a fixed and accurate sampling rate, a programmable scanning acquisition mode must be used, whose core timing is controlled by the following counters:

SI_comounter (24 bits): Scan interval=SI_comounter/Timebase (internal 40MHz or external 1-40MHz).

SI2-Counter (16 bits): Channel sampling interval=SI2-Counter/Timebase.

NumChan_comounter (9 bits): The number of samples per scan (i.e. channel gain queue length).

PSC_counter (24 bits): The number of scans collected after triggering.

M6ounter (16 bits): The number of scans stored before triggering in the pre trigger/mid trigger.

Temporal constraint: SI_comount ≥ SI2-Count × NumChan_comount, and the maximum sampling rate is limited by the model (2204/2208 is 3MS/s for single channel, 1MS/s for multiple channels; 2205 is 500kS/s; 2206 is 250kS/s. For example, when using internal 40MHz in 2204, the minimum SI2 is 14 (≈ 2.86 μ s/point).

Five triggering modes:

Software trigger: Start immediately, suitable for simple applications.

Post trigger: Collect PSC_counter scans after triggering.

Delay trigger: After triggering, the data is collected with a delay of Delay_counter clock cycles. The delay clock can be either Timebase or sampling clock.

Pre trigger: Continuously collect data before triggering, stop after triggering, and only retain the last M-counter scans. The 'enable' bit can forcibly ignore premature triggering to ensure a complete M-scan.

Middle trigger: Collect M-scan before triggering and N-scan after triggering (PSC_counter=N), also supporting M-enable.

Engineering Tip: In pre trigger and mid trigger modes, if the trigger occurs in the middle of the scan, the current scan will be completed before stopping to ensure that the data is aligned with the complete scan. The Re trigger function can be triggered multiple times in post/delay mode, with a fixed number of scans collected each time, making it very suitable for recording sudden signals.

DMA data transfer and high-performance continuous acquisition

High speed data acquisition must rely on bus master DMA. This card supports DMA with scatter/gather function, which can link multiple discontinuous memory blocks into a linked list, breaking through the limitation of continuous large memory allocation. The maximum transfer volume is only limited by system memory and PCI bandwidth. After DMA startup, the hardware automatically moves FIFO data to the host, with almost zero CPU load. The sampling rate of 2204/2208 is as high as 3MS/s, and the FIFO has 1024 samples. If not DMA transferred in time, it is prone to overflow.

Scatter/Aggregation Mechanism: The PCI controller supports 64 bit addresses, with each descriptor containing the PCI address, transfer size, and next descriptor pointer. Users can allocate multiple small buffers and chain manage them to achieve uninterrupted data flow. This method is particularly suitable for environments such as Windows/Linux where it is difficult to allocate large contiguous memory blocks.

Analog output: waveform generation and iterative control

(Note: The 2208 model does not have this function)

Dual channel 12 bit D/A, maximum update rate 1MS/s, built-in 1k word (single channel) or 512 word (dual channel) FIFO. The output range can be selected as internal ± 10V, 0~10V, or external reference (± 10V). Supports two modes: immediate software updates and timed waveform generation.

The waveform generation timing is finely controlled by the following counters:

UI_comounter (24 bits): Update interval=UI_comounter/Timebase (minimum 40, i.e. 1MHz).

UC_comounter (24 bits): The number of update points for a single waveform.

IC_comounter (24 bits): The number of waveform iterations (finite or infinite).

DA-DLY1_counter: Trigger to first update delay.

DA-DLY2-Counter: Interval between two iterations.

Trigger mode: post trigger, delayed trigger, and support for re trigger (generating a waveform once per trigger). The stop mode provides three options: immediate stop, stop after completing the current waveform, and stop after completing integer multiple iterations, flexibly responding to different termination requirements.

Engineering application: With the help of delay triggering and external reference, modulation signals synchronized with external events can be generated. If the waveform data is smaller than FIFO, repeated waveforms do not occupy PCI bandwidth, greatly improving system efficiency.

Universal Timer/Counter (GPTC): 8 modes covering measurement and control

(2208 does not have this function)

Two independent 16 bit timers/counters, with optional internal 40MHz or external (up to 10MHz) clock sources, supporting hardware/software control of counting direction, gating, and polarity. Provide 8 operating modes:

Mode 1 (Simple Gated Event Counting): Gated enable/disable counting, suitable for pulse counting.

Mode 2 (single cycle measurement): Measure the number of clocks in one cycle of the gate signal.

Mode 3 (single pulse width measurement): Measure the width of the gate signal high/low level.

Mode 4 (Single Gate Pulse Generation): After software startup, a single pulse with adjustable delay and width is generated when gate control is effective.

Mode 5 (Single Trigger Pulse Generation): Gated edge triggers a single pulse, ignoring subsequent triggers until restarted.

Mode 6 (Re trigger Single Pulse): Each gate edge triggers a single pulse (if the previous one was not completed, it will be ignored).

Mode 7 (single trigger continuous pulse): The first gate edge triggers a continuous periodic pulse.

Mode 8 (Continuous Gate Control Pulse): After software startup, periodic pulses are continuously generated when gate control is effective.

These modes cover the vast majority of industrial measurement and control requirements, such as frequency/cycle/pulse width measurement, pulse sequence generation, PWM, etc., and all input and output polarities are programmable and compatible with positive/negative logic devices.

Multi card synchronization and SSI/PXI trigger bus

For multi-channel expansion (such as 64 channels or more), system synchronization is crucial. This series achieves timing signal sharing between cards through SSI (System Synchronization Interface). In the PCI/PCIe version, SSI uses a 20 pin ribbon cable daisy chain connection; The PXI version directly uses the PXI trigger bus (P2 connector).

The six internal timing signals that can be synchronized include TIMEBASE, ADCONV, SCAN_START, AD_TRIG, DAWR, and DA_TRIG. Each signal can be independently set to master/slave mode, with one card serving as the master to output the signal and the remaining cards serving as slave receivers. For example, if four cards need to synchronize A/D sampling, the ADCONV of card 1 can be set as Master, and cards 2-4 can be set as Slave. After card 1 receives an external trigger to start, its ADCONV is driven by SSI/PXI to synchronously convert all slave cards, achieving consistent acquisition of multiple card channels.

External timing and control (AFI and dedicated triggering)

In addition to standard triggering, the board provides AFI [0] and AFI [1] multifunctional input pins, which can directly replace internal ADCONV, SCAN_START, or DAWR signals. For example, if an external event source generates a sampling clock (AFI [0] as ADCONV), "on-demand sampling" can be achieved without relying on internal counters. Meanwhile, the dedicated EXTDTRIG (digital trigger input) and EXTWFTRIG (waveform trigger input) support rising/falling edge triggering with a minimum pulse width of 20ns.

External time base (EXTTIMEBASE) can replace internal 40MHz and is used in scenarios that require specific non-standard sampling rates (such as synchronization with external system clocks), with a frequency range of 1-40MHz and TTL level.

Calibration and maintenance: ensuring long-term accuracy

The card is integrated with EEPROM and stores factory calibration constants at the factory. Users can use the Auto calibration function to correct offset and gain errors without the need for an external signal source (preheating for 15 minutes is required). After calibration is completed, the new constants can be saved to the user area (up to 3 sets) for quick switching at different ambient temperatures. The calibration reference source is 5.000V, with a temperature coefficient of ± 2ppm/° C and a long-term stability of 6ppm/1000 hours, ensuring long-term reliability.

Software Support and Development Suggestions

Linghua provides MAPS (Measurement, Automation, and Platform Services) software suite:

MAPS Core: Includes device drivers and ACE management tools, configurable DMA buffers, aliases, etc.

MAPS/LV: LabVIEW development library and examples.

MAPS/C: C/C++API library and a large amount of sample code.

It is recommended to use ACE's Soft Front Panel to quickly verify hardware functionality when using it for the first time. For high-speed continuous acquisition, it is necessary to enable DMA and configure the scattered/aggregated list reasonably to avoid data loss.