ADLINK DAQ/DAQE/PXI-250x waveform generation complete guide



ADLINK DAQ/DAQE/PXI-250x Series Analog Output Card Configuration and Waveform Generation

High precision, multi-channel analog output and waveform generation capabilities are crucial in the fields of industrial automation, automotive testing, biomedical, and ATE (Automated Test Equipment). ADLINK's DAQ/DAQE/PXI-250x series high-performance analog output multifunctional card is designed specifically for applications that require synchronous multi-channel waveform output and real-time acquisition. This series covers three bus specifications: PCI (DAQ), PCIe (DAQE), and PXI, including two models: 2501 (4-channel AO+8-channel AI) and 2502 (8-channel AO+4-channel AI). It supports analog output update rates of up to 1MS/s, analog input sampling rates of 400kS/s, and flexible multi trigger, DMA transfer, and synchronization interfaces. This article will provide you with a complete technical guide from hardware architecture, analog input/output configuration, waveform generation timing, triggering and synchronization, calibration, and software ecology, from selection to in-depth application.

Core architecture and signal pathway

The 250x series uses FPGA as the core control unit, integrating A/D conversion, D/A conversion, digital I/O (82C55A), general-purpose timer/counter (GPTC), and system synchronization interface (SSI). The most distinctive feature of its analog output is that the 2502 provides 8 12 bit DAC channels, divided into two D/A groups (4 channels per group); 2501 provides 4 channels (single group). The DACs within each group share the same update timing, trigger source, and stop mode, but each channel can independently select internal (± 10V or 0-10V) or external reference (± 10V range), and support fine tuning of external reference, which provides the physical basis for generating advanced waveforms such as amplitude modulation (AM).

The analog input section provides 4/8 single ended channels (2502/2501), 14 bit resolution, maximum sampling rate of 400kS/s, optional input range of bipolar ± 10V or unipolar 0-10V, and equipped with 2k sampling FIFO. Overvoltage protection ± 35V, input impedance 1G Ω | | 6pF, ensuring accurate measurement of high impedance signal sources.

Universal Digital I/O provides 24 programmable I/O channels compatible with TTL/CMOS (via 82C55A), with each port capable of independently configuring direction. The universal timer/counter provides two 16 bit independent channels and supports 8 working modes (gate counting, cycle/pulse width measurement, single pulse/continuous pulse generation, etc.). The clock source can be internal or external (up to 10MHz), which is very suitable for timing control in conjunction with analog output.

Analog input: software polling and programmable scanning

Analog input supports two modes: software polling and programmable scanning. Software polling is suitable for low-speed, single point, or random sampling. The software triggers a transition and polls the state, but it is difficult to fix the sampling rate.

Programmable scanning is suitable for continuous acquisition that requires precise and fixed sampling rates. Scanning is controlled by four counters working together:

SI_comounter (24 bits): Scan interval=SI_comounter/Timebase (internal 40MHz or external 1-40MHz).

SI2-Count (24 bits): Channel sampling interval=SI2-Count/Timebase.

PSC_counter (24 bits): The number of scans executed after triggering.

Delay_counter (16 bits): The delay time for triggering a scan.

The upper limit of the sampling rate is 400kS/s, so the minimum SI2 under the internal time base is 100. The scanning interval should be ≥ sampling interval x number of channels per scan. The scanning channel sequence can be continuous or intermittent, and can be flexibly arranged through channel gain queues. The triggering modes include post triggering, delayed triggering, and post/delayed triggering with re triggering (the re triggering signal is ignored during scanning). Data can be directly transferred to the host memory through the bus master DMA (supporting scattered/aggregated), greatly reducing CPU load and suitable for long-term high-speed acquisition.

Waveform generation: precision timing and complex waveforms

This is the core highlight of the 250x series. Its D/A group has a built-in maximum 16k (2502) or 8k (2501) sample FIFO, supporting hardware controlled waveform generation without CPU intervention, ensuring accurate update rates and not affected by system load.

1. Key counters

Six counters jointly shape the waveform:

UI_comounter (24 bits): Update interval=UI_comounter/40MHz (minimum 40, corresponding to 1MS/s).

UC_comounter (24 bits): The number of update points contained in a single waveform (i.e. the number of waveform samples).

IC_comounter (16 bits): The number of waveform iterations (finite or infinite).

DLY1_comounter (16 bits): Delay from triggering to waveform start.

DLY2_comounter (16 bits): The interval between consecutive waveform iterations.

Trig_comounter (16 bits): The number of triggers received in the re trigger mode.

2. Trigger and Iteration

The waveform generation supports post triggering (triggering starts immediately), delayed triggering (starting after delaying DLY1), and versions with repeated triggering (generating one waveform iteration sequence per trigger, repeating Trig_comounter times). The iterative mode can generate finite or infinite repeated waveforms, and DLY2 intervals can be inserted between adjacent waveforms, which is suitable for scenarios that require intermittent output.

3. Segmented generation and stopping mode

If UC_comounter is less than the actual number of waveform samples, the waveform is "segmented" and DLY2 intervals can be inserted between each segment to achieve complex function concatenation (such as sine, triangle, sawtooth sequences). Stop mode provides three options:

Mode I: Stop immediately.

Mode II: Stop after completing the current complete waveform.

Mode III: Stop after completing the current integer multiple of iterations.

Users can flexibly choose according to their needs to ensure the integrity of the output waveform.

4. Flexible application of reference sources

Each DAC can independently select an internal 10V reference or an external reference (± 10V), and the external reference can be fine tuned through the onboard calibration circuit. Using the multiplication property of DAC, output=digital code x reference voltage. If an external reference is applied with a sine wave, amplitude modulation (AM) waveform can be directly achieved. If the external reference is different DC voltages, the output range will change accordingly. All DACs within the same group are updated synchronously to ensure that there is no phase difference in the multi-channel waveform.

Advanced triggering and synchronization

Analog trigger: can come from an external EXTATRIG pin (± 10V, 8-bit resolution) or from an ADC input signal (full range). Provide five triggering conditions: below low threshold, above high threshold, within interval, high latency, low latency, support for rising/falling edge selection and programmable latency, suitable for reliable triggering in noisy environments.

Digital triggering: Supports external TTL edge triggering.

Software trigger: triggered by internal instructions.

The System Synchronization Interface (SSI) is another powerful tool in the 250x series. It provides 7 timing signals (TIMEBASE, ADCONV, DAWR, SCAN_START, AD_TRIG, DA_TRIG, etc.) that can be shared among multiple cards. Each signal can be independently set to master/slave mode: the master card outputs the signal, while the slave card receives and replaces the internal timing. In the PXI version, these signals are transmitted through the PXI trigger bus (J2); In the PCI/PCIe version, it is achieved through a dedicated 20 pin SSI connector (ribbon cable daisy chain). With SSI, users can synchronize the analog output and acquisition of dozens or even hundreds of channels, meeting the requirements of large-scale testing systems.

External auxiliary inputs (AFI0/AFI1) allow external signals to directly replace internal ADCONV, DAWR, SCAN.START, or TIMEBASE, providing unparalleled flexibility for custom sampling/update timing.

Data Transfer and DMA

Both high-speed waveform generation and continuous acquisition require bus master DMA. This card supports Scatter/Gather DMA, which can link multiple discontinuous memory buffers into a linked list, breaking the single block continuous memory limit. It is particularly effective in multitasking systems such as Windows/Linux. The maximum transmission in non chain mode is 8MB, while there is no limit in chain mode. Once DMA is started, the hardware automatically moves the FIFO data to the host, with almost no CPU involvement. For the 8-channel 1MS/s output of 2502, with a huge amount of data, DMA is the inevitable choice.

Calibration and precision maintenance

On board precision 5V reference source (temperature drift ± 2ppm/° C, long-term stability 6ppm/1000 hours), combined with TrimDAC (multi-channel DAC) and automatic calibration circuit, can compensate for bias and gain errors. Self calibration does not require external instruments and can be completed by users through software triggering. After calibration, the constants can be stored in three user storage areas of EEPROM. It is strongly recommended to preheat for 15 minutes before calibration and remove all connecting cables. The factory default constant is stored in the factory area, and the user calibration constant can be loaded or overwritten at any time, making it easy to quickly switch between different environmental temperatures.

Universal Timer/Counter (GPTC)

Two independent 16 bit timers/counters provide 8 operating modes: Simple Gate Event Counting (Mode 1), Single Cycle Measurement (Mode 2), Single Pulse Width Measurement (Mode 3), Single Gate Pulse Generation (Mode 4), Single Trigger Pulse Generation (Mode 5), Re Trigger Single Pulse (Mode 6), Single Trigger Continuous Pulse (Mode 7), and Continuous Gate Pulse (Mode 8). All input/output polarities are programmable, and gating, clock, and counting directions can be controlled by hardware or software. These modes cover common requirements such as frequency measurement, PWM generation, and pulse delay, and can be coordinated with waveform generation (such as using GPTC output as an external trigger).

Software Support and Development

Linghua provides MAPS (Measurement, Automation, and Platform Services) suite:

MAPS Core: Driver+ACE management tool, configurable DMA buffer, alias, Board ID (via SW1 DIP switch), etc.

MAPS/LV: LabVIEW Library and Examples.

MAPS/C: C/C++API and rich examples.

It is recommended that new users quickly verify hardware functionality through ACE's software panel, and then gradually delve into DMA and synchronization configuration. Board ID is disabled by default and needs to be enabled in the D2K-DASK tool for multi card recognition.

Engineering application examples

Multi channel arbitrary waveform generator: Using the 8-channel synchronous output of 2502, combined with external reference and SSI synchronous multi card, it can generate phase array signals for automotive radar testing.

Closed loop control system: AI collects controlled signals (400kS/s), calculates them through control algorithms, and outputs control quantities (1MS/s) in real-time through AO, forming a high-speed control loop.

Frequency sweep excitation response test: Using segmented generation and iterative modes, different frequency sine waves are sequentially output, with DLY2 intervals inserted between each segment, and AI is used to collect responses to achieve frequency response analysis.

AM/FM signal simulation: By using an external reference input modulation signal and combining it with an internal DAC output carrier, it directly generates amplitude modulation or frequency modulation signals for communication equipment testing.