ADLINK 7200 Series High Speed DIO Card Practical Guide

ADLINK 7200 Series High Speed DIO Card Configuration, Programming, and Engineering Practical Guide

Why choose the 7200 series? ——Hardcore requirements for high-speed digital I/O

In the fields of industrial automation, high-speed data recording, digital waveform generation, and interface conversion, engineers often face a challenge: how to achieve high-speed, reliable, and low latency digital signal acquisition and output? Traditional CPU polling or interrupt methods are difficult to meet throughput of hundreds of KB or even several MB/s, while dedicated FPGA solutions have long development cycles and high costs.

The 7200 series high-speed digital I/O cards (including PCI-7200, PCIe-7200, and cPCI-7200) launched by ADLINK are designed to solve such problems. This series provides 32 TTL digital inputs and 32 TTL digital outputs, supporting a peak transfer rate of 12MB/s. With the help of bus control DMA and onboard FIFO, it can significantly reduce CPU burden and achieve high-speed continuous data flow. This article will provide engineers with a practical reference manual that covers hardware installation, operating modes, register programming, and performance bottlenecks.

Hardware Overview and Installation Points

2.1 Board Layout and Interface Differentiation

PCI-7200/PCIe-7200: Provides a 37 pin D-Sub connector (CN2, located on the board) and a 40 pin flat cable connector (CN1, located on the front edge of the board). CN2 provides DI [0.. 15] and DO [0.. 15]; CN1 provides DI [16. 31], DO [16. 31], and handshake signals (REQ, ACK, I-TRG, O-TRG).

CPCI-7200: Adopting a 3U CompactPCI shape, it provides all 32 DI/DO channels and additional 4 auxiliary DIOs (only cPCI), Schottky terminals, and diode clamping through a rear outlet connector (CN), suitable for high noise industrial environments.

2.2 Installation process and precautions

Electrostatic protection: It is necessary to operate on a grounded anti-static workbench and wear a wristband. After unpacking, check if the IC is loose and press it firmly.

Slot selection: Any available PCI/PCIe slot is acceptable, but it is necessary to ensure that the motherboard supports Bus Mastering, otherwise DMA cannot function.

Plug and play: The 7200 series has no jumpers or switches, and the I/O base address and interrupt number are automatically assigned by the BIOS. In the Windows system, the first insertion will prompt for driver installation. It is recommended to use ADLINK's DAQPilot (new generation driver) instead of the old version DASK.

2.3 Key connector pins (commonly used in engineering)

CN2 (D-Sub 37 pin): Pin 1-32 corresponds to DI0~DI15 and DO0~DO15 (odd pin DI, even pin DO, see Figure 2-5 for details). Pin 33=GND, Pin 34=O-ACK, Pin 35=O-REQ, Pin 36=O-TRG, Pin 37=GND. Note: The I-REQ signal is on pin 19 of CN2 (PCI/PCIe version).

CN1 (40 pin flat): Provides high 16 bit channels and options such as I2 TRG, O3 TRG,+5V, etc. Please refer to Figure 2-4 in the manual for specific allocation.

Practical tip: If only the low 16 bit channel is used, simply connect CN2 and use the ACL-10437 cable (40 pin to 37 pin D-Sub) provided by ADLINK to easily connect to the standard interface.

Deep analysis of four operation modes

The core flexibility of the 7200 series lies in supporting four data transfer modes, adapting to different peripheral protocols and real-time requirements.

3.1 Direct program control (simplest)

Read and write registers directly through I/O ports:

Input: Read BASE+10 (32-bit) to obtain the current DI status.

Output: Writing BASE+14 (32-bit) can set the DO level, and after writing, the output status can be read back through the same address for easy verification.

This mode is suitable for low-speed switch detection or initialization configuration, without DMA, and the CPU directly participates in each transfer.

3.2 Internal Timer Pacer Mode (Most Commonly Used)

Utilize the onboard 8254 programmable timer/counter to generate a uniform sampling clock, trigger DI sampling or DO update, and cooperate with DMA to automatically transfer data. This is the preferred solution for achieving high-throughput continuous data collection.

Key points for timer configuration:

The clock source is 4MHz (fixed).

Timer 0 output (OUT0) serves as the DI sampling clock; Timer 1 (OUT1) serves as the DO output clock.

Support cascading: Cascading Timer 2 with Timer 0 (or Timer 2 with Timer 1) can achieve extremely low frequencies (minimum about 4MHz/(65535 * 65535) ≈ 0.00093Hz). Cascade control is set by the T0_T2 and T1_T2 bits of register BASE+1C.

Pacer frequency calculation:

When not cascaded: f_spacer=4MHz/(initial value of counter)

When cascading: f_spacer=4MHz/(initial value 0 * initial value 2)

Example: To obtain 2.5kHz, set the initial value to 0=40 and the initial value to 2=40 (4MHz/1600=2.5kHz).

Maximum internal timer rate: 2MHz (with a minimum initial value of 2, as 4MHz/2=2MHz), corresponding to 8MB/s (32-bit data, 2MHz x 4 bytes).

Operating Procedures:

Set the initial value of the timer to enable I2 TIME0 (input) or O1 TIME1 (output).

Enable I2 FIFO or O1 FIFO.

Enable DIN-IN (input) or corresponding output control.

DMA automatically transfers FIFO data to system memory without the need for CPU intervention.

Common pitfalls in engineering: If the timer rate is too high (close to 2MHz) and the system PCI bus is busy, the FIFO may overflow (input) or overflow (output). You can check the status bits I2 OVR and O2 UND (located at BASE+18) and reduce the rate appropriately or enable interrupt handling.

3.3 External clock mode (synchronous peripherals)

DI sampling is triggered by the I-REQ edge provided by an external device (which can be set as a rising edge or falling edge, through the REQ. NET bit). This mode is suitable for synchronous sampling with external ADCs, encoders, etc., with a sampling rate of up to 3MHz (12MB/s), higher than the internal timer. But external signals are needed to ensure stable edges.

Notes:

The minimum high/low level width of I-REQ needs to be ≥ 60ns, with a period of ≥ 5 PCI clock cycles (approximately ≥ 125ns, if PCI is 33MHz).

Similarly relying on DMA for data transfer, FIFO depth is limited (PCI/PCIe version only has 8 32-bit words, cPCI version has an additional 2K words input into FIFO), so bus latency still needs to be taken into account at high speeds.

3.4 Handshake mode (ensuring data integrity)

The above two modes may result in data loss due to PCI bus arbitration delay at extremely high speeds. The handshake mode uses REQ/ACK signals for flow control, ensuring that each data transaction is confirmed before sending the next one. It is the only mode that can guarantee zero data loss, and the average rate can still reach 12MB/s (but may fluctuate instantaneously).

Input handshake:

After the external device prepares the data, pull down (or up) the I2 REQ.

After sampling DI with 7200 and storing it in FIFO, automatically raise the I2 ACK (requires enabling the I2 ACK bit).

After the external device detects that the I2 ACK is valid, revoke the I2 REQ and complete a handshake.

Timing requirement: Maintain I2 REQ until I2 ACK appears and I2 ACK until I2 REQ is revoked.

Output handshake:

7200 moves DO data out of the FIFO and lowers the OREQ (OREQ needs to be enabled) when ready.

After the external device reads the data, it responds with an O-ACK (low level valid).

After detecting OACK at 7200, revoke OREQ and prepare for the next transaction.

Engineering value: Suitable for interaction with FPGA, microcontroller, old-fashioned parallel port peripherals, etc., without the need for precise clock synchronization, automatically adapting to each other's speed.

Register Programming Quick Check (Key)

Mastering the bit definitions of several key registers is the foundation of successful programming (the following base address BASE is allocated by BIOS and can be obtained using tools).

4.1 Digital input register (BASE+10, read-only)

32-bit corresponds to DI0~DI31. Read to obtain the current level.

4.2 Digital Output Register (BASE+14, read-write)

Write updates DO0~DO31, read and retrieve the current output value.

4.3 DIO Status and Control Register (BASE+18, read-write)

Core control position:

DIN-IN (bit0): Input total enable, set 1 to start sampling.

I-TRG (bit4): External trigger enable (used for external trigger start sampling, not I-REQ).

I-FIFO (bit3): Input FIFO enabled (must be set to 1 to enable DMA path).

I_TIME0 (bit2): Timer0 enabled (internal clock source).

I-REQ (bit1): External I-REQ enabled (external clock source or handshake).

I2 ACK (bit0): Input response enable (handshake mode).

Output similar to: O-TIME1, O-FIFO, O-REQ, O-ACK.

Status bits: I-OVR (input overflow), O-UND (output underflow), write 1 to clear.

4.4 Interrupt Status and Control Register (BASE+1C, read-write)

Interrupt source selection: IOUACK, II-REQ, TO-IN, T1-IN, T2-IN.

Interrupt status: SO-ACK, SI-REQ, SI_T0, SI_T1, SI_T2, write 1 clear.

Cascade control: T0_T2, T1_T2.

Polarity selection: REQ (1=effective falling edge, 0=effective rising edge).

Practical programming suggestion: If using interrupts, the corresponding interrupt status bit must be cleared in the ISR, otherwise subsequent interrupts cannot be triggered.

4.5 8254 Timer Register (BASE+0~+C)

BASE+0、 +4. +8 corresponds to the counting registers (read and write 16 bits) for Timer0, 1, and 2, respectively.

BASE+C is a control word register (write only) used to set the operating mode (recommended to use Mode 3 (square wave) or Mode 2 (rate generator)).

Double Buffer DMA Mode - Implementing Uninterrupted Interruption

For long-term high-speed data collection, a single buffer may overflow due to insufficient processing time. 7200 supports dual buffer DMA (input only), as shown in Figure 5-1: a circular buffer is allocated in the system memory, which is logically divided into two halves. DMA alternately writes data to two half regions, and when one half region is filled, switches to the other. At the same time, the application can safely process the full half region data without conflicting with the half region being written. This mechanism achieves zero copy continuous flow, which is very suitable for data recording or real-time analysis.

Key implementation points:

Double buffering mode needs to be set through the driver API (DAQPilot), and callback or event notification half filling needs to be registered.

Please note that the buffer size should be large enough to hold at least several seconds of data to prevent the application layer from processing it in a timely manner.

Performance limitations and engineering decisions

The manual clearly states several limitations that engineers must weigh when designing a system:

12MB/s is the theoretical peak, which can only be reached when 7200 monopolizes the PCI bus. In actual systems, the PCI bus may be occupied by graphics cards, network cards, etc., resulting in a decrease in actual throughput.

The internal timer or external clock mode does not guarantee data integrity because the FIFO depth is limited (PCI version only 8 words), and if the PCI bus delay exceeds the FIFO fill time, it will overflow. The only guarantee of no damage is the handshake mode.

Ensuring a rate of 1MB/s (under exclusive bus conditions) is a recommended value for reliable design. If the application requires sustained high speed without losing data, it is recommended to use handshake mode or reduce the speed.

The maximum single transmission size is 64MB. If a larger data stream is required, it needs to be transmitted multiple times or double buffered in a loop.

Engineering countermeasures:

Choosing a higher bandwidth PCIe version (PCIe-7200) can reduce bus contention, but is also limited by onboard FIFO.

For cPCI-7200, its additional 2K word input FIFO significantly enhances its ability to resist bus delay, making it a more reliable choice.

If an external clock is used and the external device is uncontrollable, an interrupt detection overflow flag can be used to promptly notify the upper layer of retransmission or alarm.

Drivers and Software Ecology - From DASK to DAQPilot

ADLINK provides two generations of drivers:

DASK (Traditional): Supports Windows Vista and earlier systems, no longer recommended.

DAQPilot (new generation): graphical driver and SDK, supporting Windows 10/11, 64 bit, providing task guidance, greatly reducing development difficulty. It is recommended that all new projects use DAQPilot and download the latest version from the official website.

In addition, ADLINK's DAQMaster tool can centrally manage all DAQ devices, view resource allocation, and test basic functions, making debugging very convenient.

Frequently Asked Questions and Troubleshooting (FAQ Style)

Q1: After installation, the system cannot recognize the device?

Check if the PCI slot is damaged and try replacing the slot; Ensure that PCI Bus Mastering is enabled in the motherboard BIOS; Manually update the driver pointing to the DAQPilot directory in the Device Manager.

Q2: Is the output frequency of the internal timer inaccurate?

Note that the clock source of 8254 is 4MHz (non-standard 1MHz or 2MHz), and when calculating the initial value, it is necessary to divide 4MHz by the expected frequency. In addition, when cascading, T0_T2 or T1_T2 bits need to be set correctly, otherwise the initial value is invalid.

Q3: Is there data loss during high-speed data acquisition (with I2/OVR set)?

The solution is to try one by one: reduce the sampling rate; Switch to handshake mode; Upgrade to cPCI version (larger FIFO); Check if the PCI bandwidth of the system is occupied by other devices (such as high load graphics cards), and try adjusting the device priority.

Q4: No response from external devices in handshake mode?

Check if the external device correctly detects OREQ and promptly returns OACK; Check if the signal level is TTL compatible (high ≥ 2.0V, low ≤ 0.8V); Check if the cable connection is open circuited; REQ/ACK timing can be observed through an oscilloscope.

Q5: How to achieve continuous long-term data collection (over 64MB)?

Use double buffer DMA mode and copy data to a larger user buffer when each half is filled, while processing data to achieve continuous streaming.