ADLINK cPCI-6965 SBC Embedded Installation and BIOS Tuning Guide

Align the hard drive components with the board to board connector (CN14) on the motherboard and press down vertically until fully embedded.

Secure the hard drive with 4 screws from the motherboard soldering surface.

Special warning: When disassembling the hard drive, be sure to hold the adapter board and pull it out vertically. Do not tilt or shake it, otherwise it is very easy to damage the board to board connector.

3.5 PMC module installation - pay attention to V (I/O) voltage matching

CPCI-6965D (8HP version) provides PMC expansion slots through DB-6965PMC adapter card. Before installation, it is necessary to confirm:

Voltage matching: The default V (I/O) of PMC slot is 3.3V (set through jumper JPX1, default short circuited 2-3 pins). If your PMC module requires a 5V signal, you must change the JPX1 jumper to pins 1-2 and move the 3.3V fail safe button on DB-6965PMC to the 5V position.

Fix the PMC module onto the DB-6965PMC adapter board, install copper pillars and brackets, then insert the components into the PMC connectors (Upper1/Upper2) on the motherboard, and finally secure them with 6 screws.

Serious warning: Voltage mismatch can permanently damage PMC modules or motherboards! Be sure to confirm repeatedly before powering on.

3.6 USB Flash Disk Module Installation (onboard reinforcement)

CN5 (9-pin pin header) is reserved on the motherboard for installing a horizontal USB flash drive module, with a maximum size of 39mm × 29mm (length × width) and a connector height of 7.4mm. During installation:

Fix the copper pillar on the bottom of the USB module.

Align the CN5 pin and mounting hole, and insert carefully.

Lock the motherboard soldering surface with screws.

This solution is more reliable than external USB drives and is suitable for system disks or critical data storage.

3.7 Inserting the whole machine into the chassis - anti misoperation and anti bending pins

The cPCI-6965 can be inserted into the system slot (as a controller) or peripheral slot (only as a PCI device) of a 6U CompactPCI chassis. Insertion steps:

Press the pop-up handle to place it in the open position.

Align the upper and lower guide rails and slowly push in. If you feel significant resistance, immediately exit and check if the back panel pins are bent. Do not forcefully insert!

Push it to level with the chassis panel, close the pop-up handle inward, and tighten the panel screws.

Watchdog Timer - The Guardian of System Never Downtime

For unmanned industrial controllers, Watchdog Timer (WDT) is the last line of defense. CPCI-6965 utilizes ITE IT8712F Super I/O (located on LPC bus 2Eh) to implement a hardware watchdog that can monitor system operation. If the application program fails to "feed the dog" on time, the hardware will automatically reset.

4.1 WDT Core Functional Parameters

Timeout range: 1 second to 15300 seconds (approximately 4.25 hours)

Trigger action: Reset the system (via KBRST signal)

Control method: Programming through registers of Super I/O

4.2 Programming points (based on example code in the manual)

Standard procedure for using a watchdog:

Enter Super I/O configuration mode: Write a specific "entry key" (0x87, 0x01, 0x55, 0x55, or 0xAA) to the address port (2Eh or 4Eh).

Select logical device: Select the WDT logical device of IT8712F through the configuration register.

Set timeout value: Write to the count register (in seconds), for example, write to tempCount.

Enable WDT: Set the enable bit in the control register (0x40 bit in the manual), and also select to enable keyboard/mouse interrupts.

Exit configuration mode: Write 0x02 to the address port and 0x02 to the data port.

Regularly 'feed the dog': repeatedly write timeout values (or re enable) in the main loop of the application to prevent the counter from resetting to zero.

Practical code snippet (from manual, C language style):
c//Enter configuration mode (taking 2Eh as an example)

outportb(0x2E, 0x87);

outportb(0x2E, 0x01);

outportb(0x2E, 0x55);

outportb(0x2E, 0x55);//Set timeout (assuming tempCount is in seconds)

outportb(0x2E, 0x71); //Select WDT control register

registerValue = inportb(0x2F);

registerValue |= 0x40; //Enable WDT to reset through KBRST

outportb(0x2F, registerValue);

outportb(0x2E, 0x73); //Set Count Register

outportb(0x2F, tempCount);//Exit configuration mode

outportb(0x2E, 0x02);

outportb(0x2F, 0x02);

Engineering suggestion: The feeding interval for dogs should be set to 1/2 to 1/3 of the timeout value, leaving enough margin to cope with sudden CPU load peaks.

5、 BIOS Fine tuning - From POST to PXE

CPCI-6965 uses AMI BIOS V8 and enters settings through the Del key. The following focuses on options closely related to industrial applications.

5.1 Boot Settings Optimization

Quick Boot: Set to Enabled to skip some memory tests and speed up power on startup (especially useful for testing devices that frequently restart).

Quiet Boot: If set to Enabled, hide POST self-test information and display OEM logo; If you need to observe the hardware self-test details, set it to Disabled.

Boot Device Priority: The priority for booting from CF cards, SATA hard drives, USB, or PCIe networks can be adjusted as needed.