Application and Configuration of ADLINK cPCI-9116 Data Acquisition Card

Detailed explanation of ADLINK cPCI-9116 data acquisition card application and configuration

In modern testing and measurement, industrial automation, and scientific research experiments, high-precision and high sampling rate data acquisition cards are the core of the system. ADLINK's cPCI-9116 series 16 bit, 250KS/s analog input card is designed specifically for the 3U CompactPCI platform, integrating rich analog and digital I/O functions, as well as flexible triggering and transmission mechanisms. This article will delve into the application technology key points of cPCI-9116 from the aspects of hardware architecture, signal connection, acquisition mode, trigger configuration, and data transmission, to help engineers quickly get started and maximize its performance.

Overview of Hardware Architecture

CPCI-9116 is a high-performance data acquisition card based on a 32-bit CompactPCI bus, which supports plug and play and does not require manual configuration of base addresses, interrupt numbers, and other resources. The core analog input channel can be configured as follows:

Up to 64 single ended (SE) inputs or 32 differential (DI) inputs;

Single ended and differential can be mixed and flexibly specified through channel gain queues;

16 bit resolution, built-in 1K word A/D FIFO buffer;

The channel gain queue depth is 512 words, and the range and input type of each channel can be independently set (bipolar ± 5V, ± 2.5V, ± 1.25V, ± 0.625V, or unipolar 0-10V, 0-5V, 0-2.5V, 0-1.25V);

The maximum sampling rate is 250KS/s, the analog input accuracy is better than 0.01% FSR (full scale), and the input impedance is as high as 100M Ω | | 6pF.

In addition, the board also provides 8 TTL digital inputs and 8 digital outputs, as well as a 16 bit universal timer/counter that supports internal 24MHz or external clock input.

Analog input signal connection and configuration

The correct signal connection is a prerequisite for obtaining accurate measurement results. The 100 pin SCSI-II connector (J1) of cPCI-9116 provides all analog, digital, and timer signals.

1. Type of signal source

Floating signal source: isolated from the system ground, such as thermocouple, transformer output, optocoupler isolated output. This type of signal requires a bias return path.

Grounding reference signal source: If the signal source is grounded with the system (such as non isolated instrument output), attention should be paid to ground loop interference.

2. Input mode selection

Single ended mode (SE): All signals are referenced to AGND, suitable for floating ground signals, with simple wiring but weak resistance to common mode noise. When multiple floating sources share the same location, the number of connections can be reduced.

Differential mode (DI): Each channel has AIH (high) and AIL (low), and the amplifier responds to the difference between the two, effectively suppressing common mode noise. For the grounding reference source, the differential mode can be directly connected (as shown in Figure 3-3); For floating ground sources, a resistor (approximately 100 times the source impedance) needs to be added between AIL and AGND to provide a bias circuit (as shown in Figure 3-4).

User common mode mode (U_CMMD): When multiple grounded reference sources are grounded together, the signal can be locally grounded to the negative input terminal, and the U_CMMD pin can be grounded to the signal ground. The common mode rejection capability of the instrument amplifier is used to eliminate the ground potential difference (as shown in Figure 3-5).

Engineering Tip: Differential mode has the best noise suppression, but reduces the number of channels by half. The mixed mode allows partial channel SE and partial DI, which need to be specified channel by channel in the channel gain queue.

A/D acquisition working mode

CPCI-9116 supports two basic acquisition modes: software polling mode and programmable scanning acquisition mode.

1. Software polling mode

The simplest way is suitable for single point or low rate requirements. The user initiates a conversion by writing a software trigger bit, and then polls the FIFO empty bit to read data when it is low. Conversion time ≤ 4 μ s, can be read directly with appropriate delay. This mode has an uncontrollable speed and is difficult to achieve a fixed sampling interval.

2. Programmable scanning acquisition mode

To achieve a fixed and accurate sampling rate, this mode must be used. Its core consists of four counters:

SI_comounter (24 bits): The scanning interval determines the time between the start of two scans.

SI_2counter (16 bits): Sampling interval, which refers to the time interval between the conversion of adjacent channels within the scan.

SC_comounter (24 bits): The number of scans collected after triggering (later triggered or middle triggered).

DIV_comounter (9 bits): The number of samples included in each scan, which is the length of the channel gain queue.

Temporal relationship: Sampling interval=SI_2counter/time base; Scan interval=SI_comounter/time base; And it is required that SI_comounter ≥ SI2-Counter × DIV_comounter. The time base can be either an internal 24MHz or an external clock (1-24MHz).

Key limitation: The maximum sampling rate is 250KS/s, so when using an internal time base, SI_2counter is ≥ 96; The maximum scanning interval is about 0.699 seconds, and the maximum inter channel sampling interval is about 2.73ms.

Channel gain queue: In scanning mode, the queue length is usually equal to DIV_comounter, and each entry in the queue specifies the channel number, gain, and input type. Collect data in sequence according to the queue order during scanning, and loop until the scan count specified by SC_comounter is met.

Example: If SI2=240 (sampling interval of 10 μ s), SI=960 (scanning interval of 40 μ s), DIV=4, and the queue order is ch1, ch2, ch0, ch2, then the actual sampling order repeats the sequence. The equivalent sampling rates ch0 and ch1 are 25kHz, and ch2 is 50kHz.

Detailed explanation of five triggering modes

External triggering is the key to synchronous collection. CPCI-9116 supports software triggering and four types of external digital triggering (rising/falling edge optional), with external triggering signals input from J1-46 (ExtTrg).

1. Software triggering

Call the function to start immediately, without external signals, suitable for regular continuous acquisition.

2. Pre trigger

Collect data from M scans before triggering. The user sets a 16 bit counter, with a total data volume of DIV_comount multiplied by the counter. When triggered, only the data from the last M scans is retained. If the trigger occurs during a scanning process, it will wait for the scan to complete before stopping to ensure that the data is aligned on a scan by scan basis.

If triggered too early (before M scans are completed), the actual data volume may be insufficient. The trigger signal can be forcibly ignored through the M-enable bit until M scans are completed before accepting the trigger, ensuring the acquisition of complete M scan data (as shown in Figure 4-5). SC_comounter must be 0 when pre triggered.

3. Middle trigger

Collect M scans before triggering and N scans after triggering (SC_comounter=N). Total data volume=DIV_comounter × (M+N). The function of M-enable is the same as pre trigger: if set to 1, ignore the trigger until the previous M scan is completed, ensuring the integrity of the data before and after. If the trigger occurs in the middle of the scan, the first scan after the trigger will be fully included (as shown in Figure 4-7).

4. Post trigger

After triggering, collect SC_comounter scans, with a total data volume of DIV_comounter multiplied by SC_comounter. Commonly seen in event triggered records.

5. Delay trigger

After triggering, wait for the specified delay before starting the collection. The delay is controlled by Delay_counter (16 bits), and the clock source can be either a time base (24MHz) or an A/D sampling clock (time base/SI2), with a maximum delay of 2.73ms or greater (if using a sampling clock). Total data volume=DIV_comounter × SC_comounter.

Re triggering function: For post triggering or delayed triggering, the number of re triggering times (Retrig_no) can be set. After each trigger, SC_comounter scans are collected and wait for the next trigger, repeating until the re triggering times are completed (as shown in Figure 4-10). Ignore triggers that arrive early during the triggering period.

A/D data transmission mode

The collected data is temporarily stored in a 1K word FIFO and must be promptly transferred to the host memory to prevent overflow. Supports three transmission methods:

EOC interrupt transmission: An interrupt is generated at the end of each A/D conversion, and ISR immediately reads a single data. Suitable for real-time processing, but CPU overhead increases with sampling rate.

FIFO Half Full Interrupt Transfer: After accumulating 512 words in the FIFO, an interrupt is triggered. The ISR reads the 512 word block at once, reducing the number of interrupts and suitable for higher sampling rates.

Bus Master DMA Transfer: Utilizing the PCI bus master capability, data can be directly written from FIFO to the host's continuous memory buffer without the need for CPU involvement, with a maximum support of 64MB bytes (32M samples). This is the best choice for high-speed data acquisition (such as approaching 250KS/s), which can maximize PCI bandwidth and reduce CPU load. However, it should be noted that the pre trigger and mid trigger modes currently only support DMA transfer (the manual states that EOC/FIFO half full does not support these two modes).

Universal Timer/Counter

In addition to A/D, the board provides a 16 bit programmable timer/counter that can be used for frequency measurement, pulse generation, or event counting. Key features:

Programmable counting direction (hardware or software control).

The clock source can be selected as internal 24MHz or external input (up to 20MHz, J1-47).

Gate control can be enabled by internal software or controlled by external hardware (J1-97).

Supports two modes:

Mode 0 (Interrupt End Count): After writing the initial value, OUT is low, and after counting to zero, OUT becomes high and remains, suitable for event counting.

Mode 1 (Divider/Square Wave): OUT is low, outputs a high pulse when counted to 1, and then automatically reloads to continuously generate pulses. Note that the initial value should be greater than 1.

This counter can be used as an independent function or in conjunction with A/D acquisition timing (such as external trigger frequency division).

Software Development and Support

ADLINK provides a comprehensive software ecosystem for cPCI-9116:

MAPS Core: includes Windows device drivers and system management tool ACE (ADLINK Connection Explorer), which can discover devices, configure DMA cache, set aliases, etc., and supports direct display of waveforms in the Soft Front Panel.

MAPS/LV: LabVIEW development support, providing libraries and examples.

MAPS/C: C/C++development support, including header files, API libraries, and a large number of sample programs.

All software is integrated into the ADLINK full-featured CD, and some commercial versions require authorization, but a 2-hour trial is provided.

Development suggestion: There is no need to manually configure interrupts and addresses during initialization, and resources can be obtained through APIs. When using scanning mode, it is essential to correctly set the values of the four counters to ensure compliance with timing constraints (SI_comounter ≥ SI2-Counter × DIV_comounter). For high-speed applications, DMA transfer is preferred and continuous large buffers are allocated.

Engineering application examples and precautions

Typical application scenarios:

Transient signal recording: Using pre trigger mode, key data (such as shocks and spikes) are retained before triggering, and stopped after triggering to fully capture the event.

Multi channel synchronous acquisition: Eliminating common mode noise through differential input, combined with channel gain queue to achieve different channels and ranges, adapting to voltage range differences.

Low frequency long-term monitoring: using external time bases or large scanning intervals to reduce data rates and extend monitoring time.

Hardware precautions:

External power supply: J1 provides+5V (maximum 500mA) and ± 15V (maximum 5mA), which can supply power to the sensor, but overload should be prevented.

Environmental temperature: working temperature 0~60 ℃, storage -20~80 ℃, humidity 5~95%, no condensation.

Electrostatic protection: Grounding and anti-static measures must be taken before operation to avoid damaging sensitive components.

Troubleshooting: If the system fails to start or works abnormally, it may be due to interrupt conflicts. Check BIOS PCI resource allocation or try changing slots.