ADLINK cPCI/PCI-8554/R: A Complete Guide from Architecture to Application



ADLINK cPCI/PCI-8554/R: A Complete Guide from Architecture to Application

In the fields of industrial automation, data acquisition, and testing measurement, multifunctional counters/timer cards play a crucial role. They are not only the cornerstone of event counting, frequency measurement, and pulse width capture, but also the key components for building complex measurement and control systems. The cPCI/PCI-8554/R series multifunctional counter/timer card launched by ADLINK Technology occupies a place in many industrial applications with its flexible architecture, powerful feature set, and reliable PCI/CompactPCI interface. This article aims to deeply analyze the hardware architecture, core configuration, key application modes, and software development points of this series of boards, providing engineers with a detailed guide from theory to practice.

Hardware Architecture Overview: The Powerful Combination of Four Core 8254

The core competitiveness of cPCI/PCI-8554/R comes from its onboard four 8254 programmable interval timer/counter chips. 8254 is an industry standard counter chip, which contains three independent 16 bit subtraction counters inside each chip. Four chips work together to provide users with a total of 12 counters (numbered 1 to 12).

These 12 counters are not simply connected in parallel, but have achieved highly flexible interconnection through careful hardware design and software configuration. The flexibility of its architecture is mainly reflected in the following aspects:

Counter type classification: Counter 1 to 10 are designed as "independent counters". This means that their clock sources and gate signals can be independently configured through software, with diverse sources. Counter 11 and 12 are defaulted to be "cascaded counters", where the output of counter 11 (COUP11) serves as the clock input of counter 12, forming a 32-bit cascaded structure, mainly used in situations where large frequency division coefficients or long timing are required. Of course, users can also change counters 11 and 12 to independent mode through onboard jumpers (JP12, JP13), allowing their clock sources to choose between internal 8MHz or external inputs (ECLK11, ECLK12).

Flexible clock system: The clock source (CLKn) of each independent counter (1-10) can be freely switched among four sources through software:

External clock source (ECLKn): An external TTL signal from a connector, suitable for synchronizing with external events.

Front stage counter output (COUPn-1): Implement cascading between counters to build 32-bit, 48 bit, or even higher resolution counter chains.

Internal clock CK1: A programmable internal clock signal that can be divided by an 8MHz fundamental frequency or the output of counter 11 (COUP11), providing additional flexibility.

Counter 10 output (COUP10): Provides a clock option for feedback from a specific counter.

Intelligent gate control and debounce: The gate control signal (GATEn) of each independent counter (1-10) can be selected as internal default enable (high level) or external signal from the connector (ExtG n). External gating is the foundation for applications such as pulse width measurement and frequency measurement. Of particular importance, the board provides optional debounce circuits for external input clocks (ECLK 1-10) and external interrupt signals (E_INT). By using onboard jumpers (JP1~JP11) and software configuration (selecting the debounce clock DB_CK), common signal jitter and spike pulses in industrial sites can be effectively filtered out, ensuring measurement accuracy and system stability. The debounce principle requires the signal to maintain a stable state for at least four DB_CK cycles in order to be recognized as an effective level change.

Dual Interrupt System: This board supports dual interrupt sources, namely the output of counter 12 (COUP12) and external interrupt input (E_INT). These two interrupt sources share an interrupt number (INT A) on the PCI bus, but can be distinguished by software querying the status register (reading _8554_Get_iRQ_Status). This design is highly suitable for complex applications that require handling both periodic timed tasks (such as watchdog) and external emergency events simultaneously.

Digital I/O and power output: In addition to powerful timing/counting functions, the board also provides 8 TTL compatible digital inputs and 8 digital outputs for basic status monitoring and control. In addition, through the 100 pin SCSI-II connector, the board also provides+12V and+5V power outputs (with a current limit of 500mA per circuit), which can directly supply power to external sensors or low-power circuits, simplifying system design.

Detailed explanation of core configuration and jumper settings

The correct configuration is a prerequisite for the stable operation of the board. The configuration method of cPCI/PCI-8554/R combines hardware jumpers and software programming.

Hardware jumpers (JP1~JP15):

JP1~JP11: Enable the debounce function corresponding to external clocks ECLK1~ECLK10 and external interrupt E_INT, respectively. When the jumper is set to 1-2 (Enable), enable debounce; When set to 2-3 (Bypass), the bypass debounce circuit is used and the signal passes directly through. The default factory setting is bypass (without debounce function).

JP12: Select the clock source for counter 11. When set to 1-2, select the external clock ECLK11; When set to 2-3 (default), select the internal 8MHz clock.

JP13: Select the clock source for counter 12. When set to 1-2, select the external clock ECLK12; When set to 2-3 (default), select the output COUP11 of counter 11.

JP14, JP15 (only cPCI-8554/R): Used to select the voltage source for the gate control signals (GATE11, GATE12) of counter 11 and counter 12, connected by default to VCC (high-level enable).

Software configuration (key API functions):

_8554Initialize: The card initialization function must be called first. It is responsible for obtaining the base address and interrupt number allocated by the PCI BIOS, and returning the number of cards present in the system.

_8554_SET_cntCLK: Select clock sources (ECLKn, COUPn-1, CK1, COUP10) for counters 1-10.

_8554_SET-CK1: Configure the source of the internal clock CK1 (8MHz baseband or COUP11).

_8554_SET-DBCLK: Configure the sampling clock DB_CK (COUP11 or 2MHz) for the debounce circuit. Note that the DB_CK frequency cannot exceed 2MHz.

_8554-Write_Counter: Write the count value to the specified counter and set its working mode (modes 0-5, corresponding to the six working modes of 8254, such as mode 2 as a frequency divider and mode 3 as a square wave generator).

_8554_Set-INT_Control: Independently enable or disable two interrupt sources (INT1 from COUP12, INT2 from E_INT).

Typical application scenarios and case analysis

This chapter will combine examples from the manual to deeply analyze several typical engineering applications, helping engineers quickly get started.

1. High precision frequency generator

Requirement: Generate an accurate, low-frequency square wave signal, such as a pulse with a period of 1 hour.

Challenge: A single 16 bit counter has a minimum output frequency of 8MHz/65536 ≈ 122Hz at an 8MHz clock, which is much higher than 0.000278Hz (1/3600).

Solution: Adopt counter cascading. In the manual example DEMO2, cascade counters 1, 2, and 3 together. Set the clock of counter 1 to internal 8MHz and the count value to 4000; The clock of counter 2 comes from COUP1, and the count value is set to 2000; The clock of counter 3 comes from COUP2, and the count value is set to 3600.

Total frequency calculation: 8000000/4000/2000/3600=1/3600 Hz. That is, COUP3 generates a pulse every 3600 seconds (1 hour).

Implementation points: In the software, it is necessary to first set the clock source of counter 2 to COUP1 and the clock source of counter 3 to COUP2 through _8554_SET-cntCLK. Then call _8554_Srite_Counter separately to set the mode and initial value of each counter (usually using mode 2 or mode 3). Gate control signal suspended (internal pull-up enabled).

2. Pulse width measurement

Requirement: Accurately measure the duration of high or low levels of an external TTL signal.

Principle: Use the gate control signal GATE to enable the counter. During the validity period of GATE, the counter counts the internal clock of a known frequency, and the pulse width is obtained by multiplying the count value by the clock period.

Solution: Taking manual DEMO3 as an example, connect the test signal to GATE1. Select an internal 2MHz clock as the clock source for counter 1. This clock can be obtained by dividing the internal 8MHz frequency by counter 2 (for example, counter 2 is set to divide by 4). At this time, the counting range of the counter is 1/2MHz=500ns, and the maximum measurable pulse width is 500ns * 65535 ≈ 32.8ms.

Implementation points: Configure counter 2 to be in frequency divider mode, generate a 2MHz clock, and use it as the clock source for counter 1 (via _8554_SET_cntCLK). Configure counter 1 as mode 0 (end of count interrupt) or mode 2 (frequency divider), with its gate source being external GATE1. When GATE1 is high, the counter starts counting; When GATE1 goes low, the counter stops. The software reads the current count value of counter 1 (_8554_ Read_Sunter), and then subtracts the current value from the initial value to obtain the count during the high-level period.

3. Frequency measurement

Requirement: Measure the frequency of an external TTL signal ranging from 1KHz to 100KHz.

Principle: The "frequency measurement method" is used, which measures the number of rising edges of the signal to be measured within a known precise time interval (gate time). Frequency=count value/gate time.

Solution: Two counters are required. A counter (such as counter 3) is used to generate accurate gate time, and its output serves as the gate signal for another counter (such as counter 1). As shown in manual DEMO4, use a cascaded or independent counter to generate a gate signal with a low pulse width of less than 0.65 seconds (ensuring that counter 1 does not overflow at a maximum frequency of 100KHz). Connect the test signal to the external clock ECLK1 of counter 1 and suggest enabling the debounce function. Counter 1 counts the rising edge of ECLK1 during the validity period of the gate signal.

Key points of implementation: Counter 3 operates in monostable or square wave mode, generating a negative pulse with precise width as GATE1. The clock source of counter 1 is set to ECLK1, and the gate source is set to external GATE1. After the gate signal ends, the software reads the count value of counter 1 and calculates the frequency to be measured based on the gate time.

4. Event counting and watchdog timer

Requirement: Count the number of internal and external events that occur within one second.

Solution: This application combines a frequency generator and an event counter. Use counters 11 and 12 (cascaded by default) as 32-bit timers, and generate a 1-second timing signal using their precise 8MHz clock. Meanwhile, using counter 1 as the event counter, the clock source is the external event signal ECLK1, and the gate signal is controlled by COUP12 (enabled within 1 second). When COUP12 outputs a high level with a width of 1 second, counter 1 starts counting external events. After 1 second, the gate control signal goes low and counter 1 stops counting. At this time, the value of counter 1 is read, which is the total number of events in that second. This mechanism can be extended to a watchdog timer: if the system does not "feed the dog" within the set time (such as resetting counter 12 through software), counter 12 will generate an interrupt (INT1), triggering a system reset or alarm. This fully utilizes the dual interrupt system of the board, providing a highly reliable system monitoring method.

Key points of software development and debugging

Initialization process: Any application must first call _8554-INitial (or W_8554-INitial under Windows). This function will fill a PCI-INFO structure, which contains the key base address (for all subsequent register operations) and the assigned IRQ number.

Cascade configuration sequence: When configuring cascade counters in software, they should be set in the order from back to front. For example, when configuring the cascading of counters 1->2->3, the mode and initial value of counter 3 should be configured first, followed by counter 2, and finally counter 1. This can avoid unexpected output jumps during the configuration process.

Interrupt Service Program: In the DOS environment, the Interrupt Service Program (ISR) needs to be written by the user and hooked through _8554-INT_Enable. In ISR, you must call _8554_Get_IRQ_Status to determine which interrupt source triggered the interrupt, and call _8554_CLR_IRQ1 or _8554_CLR_IRQ2 to clear the interrupt status after processing, otherwise the interrupt source cannot be triggered again.

De jitter configuration: When using an external clock or external interrupt in a strong electromagnetic interference (EMI) environment, it is strongly recommended to enable the de jitter function through jumper wires and select the appropriate sampling clock through _8554_S_TDBCLK. Sacrificing small response delays in exchange for system stability and data accuracy is often worthwhile in industrial settings.