Esd VME-PCM-CADDY/2 Carrier Board Integration and Troubleshooting Guide

Esd VME-PCM-CADDY/2 Carrier Board Integration and Troubleshooting Guide

In aerospace, defense electronics, and high-end industrial testing equipment, the VMEbus architecture still holds an irreplaceable position due to its excellent mechanical strength and deterministic backplane bus. However, as the system lifecycle extends, engineers often face a tricky problem: how to smoothly integrate modern high-performance PMC (PCI Mezzanine Card) modules into old systems without overturning the original VME architecture?

The VME-PCM-CADDY/2 intelligent VME carrier board provides a highly valuable hardware level solution for this pain point. It is not a simple physical adapter board, but an intelligent hub that integrates high-performance bridge chips and independent microcontrollers. This article will break out of the manual style listing and deeply analyze the technical essence of this carrier board from the dimensions of underlying bridge logic, pin configuration avoidance, initialization process, and on-site troubleshooting.

Core bridging architecture: dual guarantee of bandwidth and protocol

To stably carry two PMC modules on the VME bus, the core lies in the bridge chip between the VME and PCI buses. The VME-PCM-CADDY/2 uses the Tundra Tsi148 VME-PCI bridge, which is the technical soul of the board.

The Tsi148 bridge supports the VME64 extension standard and natively supports 2eVME and 2eSST high-speed protocols. In traditional VME systems, data throughput is often the bottleneck. The 2eSST (source synchronous transfer) protocol allows data to be transmitted in blocks at a rate of up to 320 MB/s, which is crucial for data acquisition systems that require high bandwidth. In addition, the bridge is equipped with a 4-level VME arbiter, allowing the carrier board to respond to master polling as a slave of VMEbus and actively initiate bus requests as a master, flexibly adapting to the architecture of multi master systems.

On the PCI side, the board operates on a 64 bit, 66 MHz PCI bus and only supports 3.3V signal levels. This is a hardware prerequisite that must be noted: any PMC module inserted into it must have a signal level of 3.3V. If an old PMC module with a pure 5V signal is mistakenly inserted, not only will communication fail, but the bridge chip may also be burned. To address the potential lack of 3.3V power supply in the VME backplane, the carrier board also offers an optional onboard 3.3V generation module.

Intelligent Control Core: Behind the Scenes Work of MPC8349

Many engineers may wonder why a carrier board needs to be equipped with a microcontroller up to 400 MHz? The VME-PCM-CADDY/2 is equipped with a Freescale MPC8349 processor and comes with 128 MByte of DDR2 memory with ECC checksum and 4 MByte of NOR Flash.

Its core mission is configuration and initialization. When the system is powered on or reset, MPC8349 is responsible for register configuration of Tundra Tsi148 bridge, as well as resource allocation and low-level handshake of two PMC slots. This board provides two RS-232 serial configuration interfaces, which engineers can use to capture low-level initialization logs during the system startup phase. If the system cannot recognize the PMC module, it is often not due to a broken bridge, but rather an error in the firmware of MPC8349 initializing the PCI space. In addition, the chip also supports software development libraries for real-time operating systems such as VxWorks, facilitating deep customization for advanced users.

PMC extension and P2 pin configuration (avoiding key and difficult points)

VME-PCM-CADDY/2 offers two single size (or one dual size) PMC slots, compliant with IEEE Std 1386-2001 standard. But in actual integration, the easiest place to get stuck is the I/O pin allocation of the P2 connector.

The P2 connector of the VME backplane contains a large number of user-defined I/O pins. This carrier board provides two P2 pin allocation schemes, corresponding to different ordering models:

Standard configuration (VITA 35 standard): The I/O signals of each PMC module are independently routed to pin P2 (P4V2-64ac, P4V0-64). The two PMC modules are physically isolated on P2 and do not interfere with each other.

Option '32P' (IEEE Std 1386-2001 Table 8): In this configuration, the I/O pins of the two PMC modules have 16 pins short circuited and interconnected on the P2 connector.

Troubleshooting warning: If you purchase the '32P' version of the carrier board but insert two PMC modules with conflicting output pin definitions, it can cause serious bus conflicts and even damage the module's driver chip. During on-site debugging, if a module is found to overheat or have a high communication error rate as soon as it is powered on, the primary task is to refer to the module manual and confirm whether the signal definition on the P2 side conflicts with the short-circuit logic of the carrier board.

System Integration and Hardware Initialization Troubleshooting Guide

When deploying VME-PCM-CADDY/2 to industrial environments or testing systems, engineers often encounter the following types of issues:

1. The system cannot enumerate PMC modules (VME controller cannot find devices)