ADLINK DAQ/DAQE/PXI-220x acquisition card fully configured

Scatter/Aggregation Mechanism: The PCI controller supports 64 bit addresses, with each descriptor containing the PCI address, transfer size, and next descriptor pointer. Users can allocate multiple small buffers and chain manage them to achieve uninterrupted data flow. This method is particularly suitable for environments such as Windows/Linux where it is difficult to allocate large contiguous memory blocks.

Analog output: waveform generation and iterative control

(Note: The 2208 model does not have this function)

Dual channel 12 bit D/A, maximum update rate 1MS/s, built-in 1k word (single channel) or 512 word (dual channel) FIFO. The output range can be selected as internal ± 10V, 0~10V, or external reference (± 10V). Supports two modes: immediate software updates and timed waveform generation.

The waveform generation timing is finely controlled by the following counters:

UI_comounter (24 bits): Update interval=UI_comounter/Timebase (minimum 40, i.e. 1MHz).

UC_comounter (24 bits): The number of update points for a single waveform.

IC_comounter (24 bits): The number of waveform iterations (finite or infinite).

DA-DLY1_counter: Trigger to first update delay.

DA-DLY2-Counter: Interval between two iterations.

Trigger mode: post trigger, delayed trigger, and support for re trigger (generating a waveform once per trigger). The stop mode provides three options: immediate stop, stop after completing the current waveform, and stop after completing integer multiple iterations, flexibly responding to different termination requirements.

Engineering application: With the help of delay triggering and external reference, modulation signals synchronized with external events can be generated. If the waveform data is smaller than FIFO, repeated waveforms do not occupy PCI bandwidth, greatly improving system efficiency.

Universal Timer/Counter (GPTC): 8 modes covering measurement and control

(2208 does not have this function)

Two independent 16 bit timers/counters, with optional internal 40MHz or external (up to 10MHz) clock sources, supporting hardware/software control of counting direction, gating, and polarity. Provide 8 operating modes:

Mode 1 (Simple Gated Event Counting): Gated enable/disable counting, suitable for pulse counting.

Mode 2 (single cycle measurement): Measure the number of clocks in one cycle of the gate signal.

Mode 3 (single pulse width measurement): Measure the width of the gate signal high/low level.

Mode 4 (Single Gate Pulse Generation): After software startup, a single pulse with adjustable delay and width is generated when gate control is effective.

Mode 5 (Single Trigger Pulse Generation): Gated edge triggers a single pulse, ignoring subsequent triggers until restarted.

Mode 6 (Re trigger Single Pulse): Each gate edge triggers a single pulse (if the previous one was not completed, it will be ignored).

Mode 7 (single trigger continuous pulse): The first gate edge triggers a continuous periodic pulse.

Mode 8 (Continuous Gate Control Pulse): After software startup, periodic pulses are continuously generated when gate control is effective.

These modes cover the vast majority of industrial measurement and control requirements, such as frequency/cycle/pulse width measurement, pulse sequence generation, PWM, etc., and all input and output polarities are programmable and compatible with positive/negative logic devices.

Multi card synchronization and SSI/PXI trigger bus

For multi-channel expansion (such as 64 channels or more), system synchronization is crucial. This series achieves timing signal sharing between cards through SSI (System Synchronization Interface). In the PCI/PCIe version, SSI uses a 20 pin ribbon cable daisy chain connection; The PXI version directly uses the PXI trigger bus (P2 connector).

The six internal timing signals that can be synchronized include TIMEBASE, ADCONV, SCAN_START, AD_TRIG, DAWR, and DA_TRIG. Each signal can be independently set to master/slave mode, with one card serving as the master to output the signal and the remaining cards serving as slave receivers. For example, if four cards need to synchronize A/D sampling, the ADCONV of card 1 can be set as Master, and cards 2-4 can be set as Slave. After card 1 receives an external trigger to start, its ADCONV is driven by SSI/PXI to synchronously convert all slave cards, achieving consistent acquisition of multiple card channels.

External timing and control (AFI and dedicated triggering)

In addition to standard triggering, the board provides AFI [0] and AFI [1] multifunctional input pins, which can directly replace internal ADCONV, SCAN_START, or DAWR signals. For example, if an external event source generates a sampling clock (AFI [0] as ADCONV), "on-demand sampling" can be achieved without relying on internal counters. Meanwhile, the dedicated EXTDTRIG (digital trigger input) and EXTWFTRIG (waveform trigger input) support rising/falling edge triggering with a minimum pulse width of 20ns.

External time base (EXTTIMEBASE) can replace internal 40MHz and is used in scenarios that require specific non-standard sampling rates (such as synchronization with external system clocks), with a frequency range of 1-40MHz and TTL level.