ADLINK DAQe-2000 series acquisition card calibration and synchronization

Below Low: Triggered when the signal is below the low threshold.

Above High: Triggered when the signal exceeds the high threshold.

Inside Region: Triggered when the signal is between a low threshold and a high threshold (maintaining high threshold>low threshold).

High Hysteresis: After the signal exceeds the high threshold, it needs to drop below the low threshold before resetting, used for anti jitter.

Low Hysteresis: After the signal falls below the low threshold, it needs to rise above the high threshold before resetting.

Practical suggestion: For slowly changing sensor signals (such as temperature), using hysteresis triggering can avoid repeated triggering near the threshold; For fast transients, directly using Above High with delay triggering can accurately capture the pulse front.

Multi card synchronization: hardcore configuration of SSI interface

When the system needs to expand to 8, 12, or 16 channels, multi card synchronization is the biggest challenge. This series achieves cascading of clock and trigger signals through the System Synchronization Interface (SSI) or PXI backplane (PXI model). SSI includes six key timeline lines:

SSI_TIMEBASE (Base Time Base)

SSIOADCONV (A/D conversion start)

SSI_SCAN-START (scan start)

SSI_AD_TRIG (A/D triggered)

SSI-DAWR (D/A update)

SSI_CA_TRIG (D/A triggered)

4.1 Master slave setting rules

Each signal line can only have one master device, the rest are slave devices or disabled.

The main device can be different cards - for example, card 1 provides ADCONV, card 2 provides DA_TRIG, and they are independent of each other.

The device must be configured to receive the corresponding SSI signal and replace the internal corresponding signal source.

4.2 Synchronization Implementation Steps (Taking 4-card 16 channel synchronous acquisition as an example)

Connect the SSI interfaces of all cards through dedicated ribbon cables (PCI models) or PXI trigger buses.

Select card 1 as SSI_TIMEBASE master (outputting internal 40 MHz) and SSI_ADCONV master (outputting its internally generated conversion pulses).

Cards 2-4 are set as slave and receive SSI_TIMEBASE and SSI_ADCONV respectively.

All cards are set to the same SI_Counter (which determines the sampling interval) and PSC_Counter, and configured for post trigger mode.

Only card 1 enables external digital triggering (EXTDTRIG), and the triggering source for the rest of the cards is set to "SSI_AD_TRIG" (i.e. following the triggering of card 1).

Start DMA transfer for all cards and then send an external trigger signal. At this time, all cards are synchronously converted under the same ADCONV edge, and the phase deviation between channels is less than 2 ns (determined by the internal delay of FPGA).

Common error: Forgetting to switch the trigger source of the slave card to SSI, resulting in the slave card still waiting for independent triggering; Or TIMEBASE master-slave inconsistency, causing sampling rate offset.

D/A waveform generation and stop mode

This series provides two 12 bit D/A outputs with a maximum update rate of 1 MS/s and an onboard 2K sampling FIFO (single channel mode). Waveform generation involves four counters:

UI_Cunter: Update interval (unit: TIMEBASE cycle)

UC_Cunter: Number of points for a single waveform update

IC_Cunter: Number of waveform iterations

DA-DLY1_Counter: Delay start after triggering

DA-DLY2-Count: Interval between two iterations

5.1 Iteration and Re triggering

Setting IC_Cunter can achieve a finite number of waveform loops, and if set to 0, it will loop infinitely. After enabling re triggering, each external trigger edge initiates a complete waveform sequence (controlled by DA_SLY1), but if the previous waveform has not ended, the new trigger will be ignored.

5.2 Three Stop Modes (Software Abort)

Stop mode I: Immediately terminate the output (clamp the output to 0V).

Stop Mode II: Wait for the complete output of the current single waveform (UC_Cunter points) before stopping.

Stop mode III: Wait for integer multiples of IC_Cunter iteration cycles to complete before stopping, ensuring waveform phase continuity.

Application suggestion: In motor control testing, using stop mode II can avoid output truncation and overshoot; In batch waveform repetition, mode III can align the end phase with the start phase.

Quick troubleshooting for common faults

Possible causes and solutions for the phenomenon

External trigger invalid trigger polarity setting error; Pulse width less than 20ns; EXTDTRIG level non TTL check software polarity (rising/falling edge); Confirm the pulse width with an oscilloscope; Ensure that the high level is greater than 2.0V

Multi card data phase offset SSI clock line incorrect master-slave allocation; Excessive cable length causes edge delay. TIMEBASE and ADCONV are both in master-slave configuration; Use equal length cables; Enable edge re alignment in FPGA (driver support required)

Single ended input was used to simulate excessive measurement noise; Floating source without bias resistor; Switching to differential mode for grounding loop; Add a 100k Ω~1M Ω resistor to AIGND; Connect the sensor ground directly to the AI terminal and connect it to the ground at a single point