ADLINK DAQe-2000 series acquisition card calibration and synchronization



ADLINK DAQe-2000 Series Acquisition Card Calibration and Synchronization: Engineer's Practical Guide

In scenarios such as automated testing, biomedical signal recording, and transient waveform analysis, the DAQe-2000 series (including DAQe-2010, DAQe-2005, DAQe-2006, DAQe-2016) has become the core device for data acquisition due to its 4-channel synchronous differential input, high sampling rate of up to 2 MS/s, and flexible triggering mechanism. However, engineers often face issues such as signal drift, multi card phase misalignment, and unreliable trigger response during actual deployment. This article is based on the underlying logic of the hardware series, outlining the complete configuration path from signal access to system synchronization, and providing troubleshooting methods for typical faults.

Signal connection and grounding: the key to the success or failure of differential measurement

All models in this series offer 4-channel differential analog inputs, supporting bipolar and unipolar ranges of ± 10V, ± 5V, ± 2.5V, ± 1.25V, and 0-10V. Correctly identifying the type of signal source is the first step in avoiding common mode interference.

1.1 Ground source vs. floating ground source

Grounding reference source (such as non isolated instrument output): Its reference ground is already connected to the system ground. At this point, differential input mode should be used and the negative terminal of the signal should be connected to AI GND (note: not short circuited to instrument ground, but through a high impedance path). This mode can provide a common mode rejection ratio of 85-97 dB (DC~60Hz), effectively suppressing power frequency noise.

Floating ground sources (such as thermocouples and isolation transformers): It is necessary to add a bias return resistor at the input end (recommended to have a resistance value of 100 times the source impedance). If the source impedance is below 100 Ω, the negative terminal can be directly connected to AI GND. Never let the floating ground source hang in single ended mode, otherwise it will introduce DC offset.

1.2 Limitations of Single ended Mode

Although the card supports single ended connection (connecting all negative terminals together to AIGND), this method significantly reduces noise resistance. Unless the number of channels is tight and the signal amplitude is much larger than the noise, it is strongly recommended to use differential methods. In practical projects, when multi-channel synchronous sampling is performed, the differential connection method can increase the effective bit count (ENOB) by 0.5 to 1 bit.

Trigger mode selection: from pre trigger to re trigger

The triggering mechanism is the core of collecting timing. This series offers four A/D trigger modes, which need to be matched according to the application scenario.

2.1 Pre trigger

Suitable for capturing data before triggering events (such as waveforms before faults). It is necessary to set the M-Counter (16 bits) to specify the number of scans stored before triggering. Key points:

If the external trigger arrives too early (before completing M scans), the early trigger can be forcibly ignored by setting M1 to 1 to ensure that there are M valid data in the cache. If M-Enable=0, only the amount of data that existed before the trigger is stored, which may result in insufficient cache.

In pre trigger mode, PSC_Count must be set to 0, and the total data volume is equal to the number of enabled channels multiplied by M.Counter.

2.2 Middle trigger

Simultaneously collect data before and after triggering. M-Counter controls the number of scans before triggering, while PSC-Count controls the number of scans after triggering. Also affected by M-Enable. Note: In this mode, the M-Counter count terminates before the trigger signal (unlike pre triggering, which terminates at or before the trigger edge). During actual programming, attention should be paid to differences in software libraries.

2.3 Post trigger and Delay trigger

Post triggering is the most commonly used mode - collecting PSC_Count pen scan data after triggering. Delay triggering uses Delay_Counter (16 bits) to insert a controllable delay between triggering and acquisition, and the delay clock can be selected from TIMEBASE (40 MHz) or A/D sampling clock (TIMEBASE/SI_Count). If TIMEBASE is selected, the maximum delay is 1.638 ms; if sampling clock is selected, the delay range can be greatly expanded, suitable for scenarios where interference pulses need to be avoided.

2.4 Re trigger

On the basis of post trigger or delayed trigger, set Retrig_no, collect PSC pen data after each trigger, and then wait for the next trigger edge. During the re triggering process, if a new triggering pulse arrives before the current batch acquisition is completed, it will be ignored. This function is suitable for equal angle sampling triggered once per rotation of rotating machinery.

Five conditions and sensitivity settings for analog triggering

The analog trigger source can come from an external EXTATRIG pin (± 10V range, 8-bit resolution, approximately 78 mV step) or an internal ADC input channel (full-scale range, 256 level segmentation). The software can configure five triggering conditions:

Below Low: Triggered when the signal is below the low threshold.

Above High: Triggered when the signal exceeds the high threshold.

Inside Region: Triggered when the signal is between a low threshold and a high threshold (maintaining high threshold>low threshold).

High Hysteresis: After the signal exceeds the high threshold, it needs to drop below the low threshold before resetting, used for anti jitter.

Low Hysteresis: After the signal falls below the low threshold, it needs to rise above the high threshold before resetting.

Practical suggestion: For slowly changing sensor signals (such as temperature), using hysteresis triggering can avoid repeated triggering near the threshold; For fast transients, directly using Above High with delay triggering can accurately capture the pulse front.

Multi card synchronization: hardcore configuration of SSI interface

When the system needs to expand to 8, 12, or 16 channels, multi card synchronization is the biggest challenge. This series achieves cascading of clock and trigger signals through the System Synchronization Interface (SSI) or PXI backplane (PXI model). SSI includes six key timeline lines:

SSI_TIMEBASE (Base Time Base)

SSIOADCONV (A/D conversion start)

SSI_SCAN-START (scan start)

SSI_AD_TRIG (A/D triggered)

SSI-DAWR (D/A update)

SSI_CA_TRIG (D/A triggered)

4.1 Master slave setting rules

Each signal line can only have one master device, the rest are slave devices or disabled.

The main device can be different cards - for example, card 1 provides ADCONV, card 2 provides DA_TRIG, and they are independent of each other.

The device must be configured to receive the corresponding SSI signal and replace the internal corresponding signal source.

4.2 Synchronization Implementation Steps (Taking 4-card 16 channel synchronous acquisition as an example)

Connect the SSI interfaces of all cards through dedicated ribbon cables (PCI models) or PXI trigger buses.

Select card 1 as SSI_TIMEBASE master (outputting internal 40 MHz) and SSI_ADCONV master (outputting its internally generated conversion pulses).

Cards 2-4 are set as slave and receive SSI_TIMEBASE and SSI_ADCONV respectively.

All cards are set to the same SI_Counter (which determines the sampling interval) and PSC_Counter, and configured for post trigger mode.

Only card 1 enables external digital triggering (EXTDTRIG), and the triggering source for the rest of the cards is set to "SSI_AD_TRIG" (i.e. following the triggering of card 1).

Start DMA transfer for all cards and then send an external trigger signal. At this time, all cards are synchronously converted under the same ADCONV edge, and the phase deviation between channels is less than 2 ns (determined by the internal delay of FPGA).

Common error: Forgetting to switch the trigger source of the slave card to SSI, resulting in the slave card still waiting for independent triggering; Or TIMEBASE master-slave inconsistency, causing sampling rate offset.

D/A waveform generation and stop mode

This series provides two 12 bit D/A outputs with a maximum update rate of 1 MS/s and an onboard 2K sampling FIFO (single channel mode). Waveform generation involves four counters:

UI_Cunter: Update interval (unit: TIMEBASE cycle)

UC_Cunter: Number of points for a single waveform update

IC_Cunter: Number of waveform iterations

DA-DLY1_Counter: Delay start after triggering

DA-DLY2-Count: Interval between two iterations

5.1 Iteration and Re triggering

Setting IC_Cunter can achieve a finite number of waveform loops, and if set to 0, it will loop infinitely. After enabling re triggering, each external trigger edge initiates a complete waveform sequence (controlled by DA_SLY1), but if the previous waveform has not ended, the new trigger will be ignored.

5.2 Three Stop Modes (Software Abort)

Stop mode I: Immediately terminate the output (clamp the output to 0V).

Stop Mode II: Wait for the complete output of the current single waveform (UC_Cunter points) before stopping.

Stop mode III: Wait for integer multiples of IC_Cunter iteration cycles to complete before stopping, ensuring waveform phase continuity.

Application suggestion: In motor control testing, using stop mode II can avoid output truncation and overshoot; In batch waveform repetition, mode III can align the end phase with the start phase.

Quick troubleshooting for common faults

Possible causes and solutions for the phenomenon

External trigger invalid trigger polarity setting error; Pulse width less than 20ns; EXTDTRIG level non TTL check software polarity (rising/falling edge); Confirm the pulse width with an oscilloscope; Ensure that the high level is greater than 2.0V

Multi card data phase offset SSI clock line incorrect master-slave allocation; Excessive cable length causes edge delay. TIMEBASE and ADCONV are both in master-slave configuration; Use equal length cables; Enable edge re alignment in FPGA (driver support required)

Single ended input was used to simulate excessive measurement noise; Floating source without bias resistor; Switching to differential mode for grounding loop; Add a 100k Ω~1M Ω resistor to AIGND; Connect the sensor ground directly to the AI terminal and connect it to the ground at a single point

Automatic calibration failed without preheating; External cables have not been removed; Preheat for 15 minutes after the failure of the onboard benchmark and retry; Disconnect all connections; Check if the+5V power supply is stable (required 1.82A~2.52A)

The D/A output step is not smooth and the update rate exceeds 1MS/s; FIFO underload (low DMA priority) reduces UI_Cunter value (increases update interval); Increase PCIe bus latency priority in BIOS; Ensure that the DMA buffer block is sufficiently large (recommended ≥ 2K samples)

GPTC timer does not count external clock frequencies exceeding 10MHz; Gate polarity configuration restricts external GPTC_CLK to ≤ 10MHz; Check the effective settings of Gate high/low; Use software to read the current count value and confirm