Application and Configuration of ADLINK cPCI-9116 Data Acquisition Card

Key limitation: The maximum sampling rate is 250KS/s, so when using an internal time base, SI_2counter is ≥ 96; The maximum scanning interval is about 0.699 seconds, and the maximum inter channel sampling interval is about 2.73ms.

Channel gain queue: In scanning mode, the queue length is usually equal to DIV_comounter, and each entry in the queue specifies the channel number, gain, and input type. Collect data in sequence according to the queue order during scanning, and loop until the scan count specified by SC_comounter is met.

Example: If SI2=240 (sampling interval of 10 μ s), SI=960 (scanning interval of 40 μ s), DIV=4, and the queue order is ch1, ch2, ch0, ch2, then the actual sampling order repeats the sequence. The equivalent sampling rates ch0 and ch1 are 25kHz, and ch2 is 50kHz.

Detailed explanation of five triggering modes

External triggering is the key to synchronous collection. CPCI-9116 supports software triggering and four types of external digital triggering (rising/falling edge optional), with external triggering signals input from J1-46 (ExtTrg).

1. Software triggering

Call the function to start immediately, without external signals, suitable for regular continuous acquisition.

2. Pre trigger

Collect data from M scans before triggering. The user sets a 16 bit counter, with a total data volume of DIV_comount multiplied by the counter. When triggered, only the data from the last M scans is retained. If the trigger occurs during a scanning process, it will wait for the scan to complete before stopping to ensure that the data is aligned on a scan by scan basis.

If triggered too early (before M scans are completed), the actual data volume may be insufficient. The trigger signal can be forcibly ignored through the M-enable bit until M scans are completed before accepting the trigger, ensuring the acquisition of complete M scan data (as shown in Figure 4-5). SC_comounter must be 0 when pre triggered.

3. Middle trigger

Collect M scans before triggering and N scans after triggering (SC_comounter=N). Total data volume=DIV_comounter × (M+N). The function of M-enable is the same as pre trigger: if set to 1, ignore the trigger until the previous M scan is completed, ensuring the integrity of the data before and after. If the trigger occurs in the middle of the scan, the first scan after the trigger will be fully included (as shown in Figure 4-7).

4. Post trigger

After triggering, collect SC_comounter scans, with a total data volume of DIV_comounter multiplied by SC_comounter. Commonly seen in event triggered records.

5. Delay trigger

After triggering, wait for the specified delay before starting the collection. The delay is controlled by Delay_counter (16 bits), and the clock source can be either a time base (24MHz) or an A/D sampling clock (time base/SI2), with a maximum delay of 2.73ms or greater (if using a sampling clock). Total data volume=DIV_comounter × SC_comounter.

Re triggering function: For post triggering or delayed triggering, the number of re triggering times (Retrig_no) can be set. After each trigger, SC_comounter scans are collected and wait for the next trigger, repeating until the re triggering times are completed (as shown in Figure 4-10). Ignore triggers that arrive early during the triggering period.

A/D data transmission mode

The collected data is temporarily stored in a 1K word FIFO and must be promptly transferred to the host memory to prevent overflow. Supports three transmission methods:

EOC interrupt transmission: An interrupt is generated at the end of each A/D conversion, and ISR immediately reads a single data. Suitable for real-time processing, but CPU overhead increases with sampling rate.

FIFO Half Full Interrupt Transfer: After accumulating 512 words in the FIFO, an interrupt is triggered. The ISR reads the 512 word block at once, reducing the number of interrupts and suitable for higher sampling rates.

Bus Master DMA Transfer: Utilizing the PCI bus master capability, data can be directly written from FIFO to the host's continuous memory buffer without the need for CPU involvement, with a maximum support of 64MB bytes (32M samples). This is the best choice for high-speed data acquisition (such as approaching 250KS/s), which can maximize PCI bandwidth and reduce CPU load. However, it should be noted that the pre trigger and mid trigger modes currently only support DMA transfer (the manual states that EOC/FIFO half full does not support these two modes).

Universal Timer/Counter

In addition to A/D, the board provides a 16 bit programmable timer/counter that can be used for frequency measurement, pulse generation, or event counting. Key features:

Programmable counting direction (hardware or software control).

The clock source can be selected as internal 24MHz or external input (up to 20MHz, J1-47).

Gate control can be enabled by internal software or controlled by external hardware (J1-97).

Supports two modes:

Mode 0 (Interrupt End Count): After writing the initial value, OUT is low, and after counting to zero, OUT becomes high and remains, suitable for event counting.

Mode 1 (Divider/Square Wave): OUT is low, outputs a high pulse when counted to 1, and then automatically reloads to continuously generate pulses. Note that the initial value should be greater than 1.