ADLINK DAQ/DAQE/PXI-250x waveform generation complete guide

ADLINK DAQ/DAQE/PXI-250x Series Analog Output Card Configuration and Waveform Generation

High precision, multi-channel analog output and waveform generation capabilities are crucial in the fields of industrial automation, automotive testing, biomedical, and ATE (Automated Test Equipment). ADLINK's DAQ/DAQE/PXI-250x series high-performance analog output multifunctional card is designed specifically for applications that require synchronous multi-channel waveform output and real-time acquisition. This series covers three bus specifications: PCI (DAQ), PCIe (DAQE), and PXI, including two models: 2501 (4-channel AO+8-channel AI) and 2502 (8-channel AO+4-channel AI). It supports analog output update rates of up to 1MS/s, analog input sampling rates of 400kS/s, and flexible multi trigger, DMA transfer, and synchronization interfaces. This article will provide you with a complete technical guide from hardware architecture, analog input/output configuration, waveform generation timing, triggering and synchronization, calibration, and software ecology, from selection to in-depth application.

Core architecture and signal pathway

The 250x series uses FPGA as the core control unit, integrating A/D conversion, D/A conversion, digital I/O (82C55A), general-purpose timer/counter (GPTC), and system synchronization interface (SSI). The most distinctive feature of its analog output is that the 2502 provides 8 12 bit DAC channels, divided into two D/A groups (4 channels per group); 2501 provides 4 channels (single group). The DACs within each group share the same update timing, trigger source, and stop mode, but each channel can independently select internal (± 10V or 0-10V) or external reference (± 10V range), and support fine tuning of external reference, which provides the physical basis for generating advanced waveforms such as amplitude modulation (AM).

The analog input section provides 4/8 single ended channels (2502/2501), 14 bit resolution, maximum sampling rate of 400kS/s, optional input range of bipolar ± 10V or unipolar 0-10V, and equipped with 2k sampling FIFO. Overvoltage protection ± 35V, input impedance 1G Ω | | 6pF, ensuring accurate measurement of high impedance signal sources.

Universal Digital I/O provides 24 programmable I/O channels compatible with TTL/CMOS (via 82C55A), with each port capable of independently configuring direction. The universal timer/counter provides two 16 bit independent channels and supports 8 working modes (gate counting, cycle/pulse width measurement, single pulse/continuous pulse generation, etc.). The clock source can be internal or external (up to 10MHz), which is very suitable for timing control in conjunction with analog output.

Analog input: software polling and programmable scanning

Analog input supports two modes: software polling and programmable scanning. Software polling is suitable for low-speed, single point, or random sampling. The software triggers a transition and polls the state, but it is difficult to fix the sampling rate.

Programmable scanning is suitable for continuous acquisition that requires precise and fixed sampling rates. Scanning is controlled by four counters working together:

SI_comounter (24 bits): Scan interval=SI_comounter/Timebase (internal 40MHz or external 1-40MHz).

SI2-Count (24 bits): Channel sampling interval=SI2-Count/Timebase.

PSC_counter (24 bits): The number of scans executed after triggering.

Delay_counter (16 bits): The delay time for triggering a scan.

The upper limit of the sampling rate is 400kS/s, so the minimum SI2 under the internal time base is 100. The scanning interval should be ≥ sampling interval x number of channels per scan. The scanning channel sequence can be continuous or intermittent, and can be flexibly arranged through channel gain queues. The triggering modes include post triggering, delayed triggering, and post/delayed triggering with re triggering (the re triggering signal is ignored during scanning). Data can be directly transferred to the host memory through the bus master DMA (supporting scattered/aggregated), greatly reducing CPU load and suitable for long-term high-speed acquisition.

Waveform generation: precision timing and complex waveforms

This is the core highlight of the 250x series. Its D/A group has a built-in maximum 16k (2502) or 8k (2501) sample FIFO, supporting hardware controlled waveform generation without CPU intervention, ensuring accurate update rates and not affected by system load.

1. Key counters

Six counters jointly shape the waveform:

UI_comounter (24 bits): Update interval=UI_comounter/40MHz (minimum 40, corresponding to 1MS/s).

UC_comounter (24 bits): The number of update points contained in a single waveform (i.e. the number of waveform samples).

IC_comounter (16 bits): The number of waveform iterations (finite or infinite).

DLY1_comounter (16 bits): Delay from triggering to waveform start.

DLY2_comounter (16 bits): The interval between consecutive waveform iterations.

Trig_comounter (16 bits): The number of triggers received in the re trigger mode.

2. Trigger and Iteration

The waveform generation supports post triggering (triggering starts immediately), delayed triggering (starting after delaying DLY1), and versions with repeated triggering (generating one waveform iteration sequence per trigger, repeating Trig_comounter times). The iterative mode can generate finite or infinite repeated waveforms, and DLY2 intervals can be inserted between adjacent waveforms, which is suitable for scenarios that require intermittent output.