ADLINK 7200 Series High Speed DIO Card Practical Guide

ADLINK 7200 Series High Speed DIO Card Configuration, Programming, and Engineering Practical Guide

Why choose the 7200 series? ——Hardcore requirements for high-speed digital I/O

In the fields of industrial automation, high-speed data recording, digital waveform generation, and interface conversion, engineers often face a challenge: how to achieve high-speed, reliable, and low latency digital signal acquisition and output? Traditional CPU polling or interrupt methods are difficult to meet throughput of hundreds of KB or even several MB/s, while dedicated FPGA solutions have long development cycles and high costs.

The 7200 series high-speed digital I/O cards (including PCI-7200, PCIe-7200, and cPCI-7200) launched by ADLINK are designed to solve such problems. This series provides 32 TTL digital inputs and 32 TTL digital outputs, supporting a peak transfer rate of 12MB/s. With the help of bus control DMA and onboard FIFO, it can significantly reduce CPU burden and achieve high-speed continuous data flow. This article will provide engineers with a practical reference manual that covers hardware installation, operating modes, register programming, and performance bottlenecks.

Hardware Overview and Installation Points

2.1 Board Layout and Interface Differentiation

PCI-7200/PCIe-7200: Provides a 37 pin D-Sub connector (CN2, located on the board) and a 40 pin flat cable connector (CN1, located on the front edge of the board). CN2 provides DI [0.. 15] and DO [0.. 15]; CN1 provides DI [16. 31], DO [16. 31], and handshake signals (REQ, ACK, I-TRG, O-TRG).

CPCI-7200: Adopting a 3U CompactPCI shape, it provides all 32 DI/DO channels and additional 4 auxiliary DIOs (only cPCI), Schottky terminals, and diode clamping through a rear outlet connector (CN), suitable for high noise industrial environments.

2.2 Installation process and precautions

Electrostatic protection: It is necessary to operate on a grounded anti-static workbench and wear a wristband. After unpacking, check if the IC is loose and press it firmly.

Slot selection: Any available PCI/PCIe slot is acceptable, but it is necessary to ensure that the motherboard supports Bus Mastering, otherwise DMA cannot function.

Plug and play: The 7200 series has no jumpers or switches, and the I/O base address and interrupt number are automatically assigned by the BIOS. In the Windows system, the first insertion will prompt for driver installation. It is recommended to use ADLINK's DAQPilot (new generation driver) instead of the old version DASK.

2.3 Key connector pins (commonly used in engineering)

CN2 (D-Sub 37 pin): Pin 1-32 corresponds to DI0~DI15 and DO0~DO15 (odd pin DI, even pin DO, see Figure 2-5 for details). Pin 33=GND, Pin 34=O-ACK, Pin 35=O-REQ, Pin 36=O-TRG, Pin 37=GND. Note: The I-REQ signal is on pin 19 of CN2 (PCI/PCIe version).

CN1 (40 pin flat): Provides high 16 bit channels and options such as I2 TRG, O3 TRG,+5V, etc. Please refer to Figure 2-4 in the manual for specific allocation.

Practical tip: If only the low 16 bit channel is used, simply connect CN2 and use the ACL-10437 cable (40 pin to 37 pin D-Sub) provided by ADLINK to easily connect to the standard interface.

Deep analysis of four operation modes

The core flexibility of the 7200 series lies in supporting four data transfer modes, adapting to different peripheral protocols and real-time requirements.

3.1 Direct program control (simplest)

Read and write registers directly through I/O ports:

Input: Read BASE+10 (32-bit) to obtain the current DI status.

Output: Writing BASE+14 (32-bit) can set the DO level, and after writing, the output status can be read back through the same address for easy verification.

This mode is suitable for low-speed switch detection or initialization configuration, without DMA, and the CPU directly participates in each transfer.

3.2 Internal Timer Pacer Mode (Most Commonly Used)

Utilize the onboard 8254 programmable timer/counter to generate a uniform sampling clock, trigger DI sampling or DO update, and cooperate with DMA to automatically transfer data. This is the preferred solution for achieving high-throughput continuous data collection.

Key points for timer configuration:

The clock source is 4MHz (fixed).

Timer 0 output (OUT0) serves as the DI sampling clock; Timer 1 (OUT1) serves as the DO output clock.

Support cascading: Cascading Timer 2 with Timer 0 (or Timer 2 with Timer 1) can achieve extremely low frequencies (minimum about 4MHz/(65535 * 65535) ≈ 0.00093Hz). Cascade control is set by the T0_T2 and T1_T2 bits of register BASE+1C.

Pacer frequency calculation:

When not cascaded: f_spacer=4MHz/(initial value of counter)

When cascading: f_spacer=4MHz/(initial value 0 * initial value 2)

Example: To obtain 2.5kHz, set the initial value to 0=40 and the initial value to 2=40 (4MHz/1600=2.5kHz).

Maximum internal timer rate: 2MHz (with a minimum initial value of 2, as 4MHz/2=2MHz), corresponding to 8MB/s (32-bit data, 2MHz x 4 bytes).

Operating Procedures:

Set the initial value of the timer to enable I2 TIME0 (input) or O1 TIME1 (output).

Enable I2 FIFO or O1 FIFO.

Enable DIN-IN (input) or corresponding output control.

DMA automatically transfers FIFO data to system memory without the need for CPU intervention.