ADLINK 7200 Series High Speed DIO Card Practical Guide

Common pitfalls in engineering: If the timer rate is too high (close to 2MHz) and the system PCI bus is busy, the FIFO may overflow (input) or overflow (output). You can check the status bits I2 OVR and O2 UND (located at BASE+18) and reduce the rate appropriately or enable interrupt handling.

3.3 External clock mode (synchronous peripherals)

DI sampling is triggered by the I-REQ edge provided by an external device (which can be set as a rising edge or falling edge, through the REQ. NET bit). This mode is suitable for synchronous sampling with external ADCs, encoders, etc., with a sampling rate of up to 3MHz (12MB/s), higher than the internal timer. But external signals are needed to ensure stable edges.

Notes:

The minimum high/low level width of I-REQ needs to be ≥ 60ns, with a period of ≥ 5 PCI clock cycles (approximately ≥ 125ns, if PCI is 33MHz).

Similarly relying on DMA for data transfer, FIFO depth is limited (PCI/PCIe version only has 8 32-bit words, cPCI version has an additional 2K words input into FIFO), so bus latency still needs to be taken into account at high speeds.

3.4 Handshake mode (ensuring data integrity)

The above two modes may result in data loss due to PCI bus arbitration delay at extremely high speeds. The handshake mode uses REQ/ACK signals for flow control, ensuring that each data transaction is confirmed before sending the next one. It is the only mode that can guarantee zero data loss, and the average rate can still reach 12MB/s (but may fluctuate instantaneously).

Input handshake:

After the external device prepares the data, pull down (or up) the I2 REQ.

After sampling DI with 7200 and storing it in FIFO, automatically raise the I2 ACK (requires enabling the I2 ACK bit).

After the external device detects that the I2 ACK is valid, revoke the I2 REQ and complete a handshake.

Timing requirement: Maintain I2 REQ until I2 ACK appears and I2 ACK until I2 REQ is revoked.

Output handshake:

7200 moves DO data out of the FIFO and lowers the OREQ (OREQ needs to be enabled) when ready.

After the external device reads the data, it responds with an O-ACK (low level valid).

After detecting OACK at 7200, revoke OREQ and prepare for the next transaction.

Engineering value: Suitable for interaction with FPGA, microcontroller, old-fashioned parallel port peripherals, etc., without the need for precise clock synchronization, automatically adapting to each other's speed.

Register Programming Quick Check (Key)

Mastering the bit definitions of several key registers is the foundation of successful programming (the following base address BASE is allocated by BIOS and can be obtained using tools).

4.1 Digital input register (BASE+10, read-only)

32-bit corresponds to DI0~DI31. Read to obtain the current level.

4.2 Digital Output Register (BASE+14, read-write)

Write updates DO0~DO31, read and retrieve the current output value.

4.3 DIO Status and Control Register (BASE+18, read-write)

Core control position:

DIN-IN (bit0): Input total enable, set 1 to start sampling.

I-TRG (bit4): External trigger enable (used for external trigger start sampling, not I-REQ).

I-FIFO (bit3): Input FIFO enabled (must be set to 1 to enable DMA path).

I_TIME0 (bit2): Timer0 enabled (internal clock source).

I-REQ (bit1): External I-REQ enabled (external clock source or handshake).

I2 ACK (bit0): Input response enable (handshake mode).

Output similar to: O-TIME1, O-FIFO, O-REQ, O-ACK.

Status bits: I-OVR (input overflow), O-UND (output underflow), write 1 to clear.

4.4 Interrupt Status and Control Register (BASE+1C, read-write)

Interrupt source selection: IOUACK, II-REQ, TO-IN, T1-IN, T2-IN.

Interrupt status: SO-ACK, SI-REQ, SI_T0, SI_T1, SI_T2, write 1 clear.

Cascade control: T0_T2, T1_T2.

Polarity selection: REQ (1=effective falling edge, 0=effective rising edge).

Practical programming suggestion: If using interrupts, the corresponding interrupt status bit must be cleared in the ISR, otherwise subsequent interrupts cannot be triggered.

4.5 8254 Timer Register (BASE+0~+C)

BASE+0、 +4. +8 corresponds to the counting registers (read and write 16 bits) for Timer0, 1, and 2, respectively.

BASE+C is a control word register (write only) used to set the operating mode (recommended to use Mode 3 (square wave) or Mode 2 (rate generator)).

Double Buffer DMA Mode - Implementing Uninterrupted Interruption

For long-term high-speed data collection, a single buffer may overflow due to insufficient processing time. 7200 supports dual buffer DMA (input only), as shown in Figure 5-1: a circular buffer is allocated in the system memory, which is logically divided into two halves. DMA alternately writes data to two half regions, and when one half region is filled, switches to the other. At the same time, the application can safely process the full half region data without conflicting with the half region being written. This mechanism achieves zero copy continuous flow, which is very suitable for data recording or real-time analysis.

Key implementation points:

Double buffering mode needs to be set through the driver API (DAQPilot), and callback or event notification half filling needs to be registered.

Please note that the buffer size should be large enough to hold at least several seconds of data to prevent the application layer from processing it in a timely manner.