ADLINK PCIe-7396 Digital I/O Card Deployment Guide

ADLINK PCIe-7396 96 Channel Digital I/O Card Deployment and Configuration Guide

In the fields of industrial automation control, equipment status monitoring, and parallel data acquisition, the reliability and flexibility of high-density digital I/O channels directly determine the system response speed and scalability. ADLINK's PCIe-7396 is a 96 bit parallel digital I/O card based on the PCI Express bus. It provides up to 12 8-bit ports through 2 to 4 8255 programmable peripheral interface (PPI) chips onboard, each port can be independently configured as an input or output, and supports 48mA high current drive, external trigger acquisition, change of state (COS) interrupt, and dual interrupt source system. This article provides a complete deployment and development reference for system integration engineers, starting from hardware installation, register programming, interrupt configuration, timing/counter applications, and common debugging points.

Overview of Card Board and Hardware Installation

PCIe-7396 adopts PCI Express x1 interface, which complies with plug and play specifications. The system BIOS automatically allocates I/O addresses and IRQ resources without manual jumper settings. Its core specifications include:

I/O channel: 96 TTL compatible digital I/O channels, led out through a 100 pin SCSI connector (AMP 787082-9)

Drive capability: minimum output high level 2.4V (typical 5V), maximum output low level 0.5V; high current up to 48mA/channel, pulling current 15mA/channel

Input threshold: High level 2.0~5.25V, low level 0~0.8V, input leakage current ± 8mA

Timer/Counter: 1 8254 programmable timer/counter chip, supporting cascaded 32-bit timers and event counters

Interrupt system: Dual interrupt sources (INT1/INT2), optional COS interrupt, edge triggered interrupt, or timed/counted interrupt

Power consumption: Typical 450mA (+3.3V or+5V depending on PCIe slot power supply)

Size: 138.96 × 98.4 mm (half height PCB)

Installation steps:

Turn off the PC power, remove the chassis cover, and select an idle PCIe x1/x4/x8/x16 slot.

Touch the metal of the chassis to release static electricity, hold the edge of the card board, do not touch the components and gold fingers.

Insert the card board into the slot and press it firmly, then fix it to the chassis cover with screws.

If you need to use an external terminal board (DIN-100S direct connection, DIN-96DI isolated input, DIN-96DO isolated output), connect the SCSI cable as needed.

After powering on, the operating system automatically recognizes the device and installs the ADLINK MAPS Core driver package (download the latest version from the official website).

Attention: By default, all I/O ports on the card board are powered on to a low level (which can be independently configured to a high level or floating through jumpers JA1~JC4, as detailed below).

Connector and Port Mapping

The 100 pin SCSI connector (CN1) provides all 96 I/O points, and its pin naming convention is PnXb:

n: PPI number (1-4)

X: Port names (A, B, C), each PPI contains 3 8-bit ports

b: Position number (0~7)

For example, P1C4 represents the 4th bit of port C in PPI1. The connector provides two dedicated signals simultaneously:

Pin 99 (EXTTRG): External trigger input used to synchronously capture digital input data

Pin 51 (EVENT): External event source, connected to the input of counter # 0 8254

Port allocation:

PPI1: P1A (pins 1-8) P1B（9~16）、P1C（17~24）

PPI2：P2A（26~33）、P2B（34~41）、P2C（42~49）

PPI3: P3A (51~58), P3B (59~66), P3C (67~74) - where P3A's Pin51 is reused as EVENT

PPI4: P4A (76~83), P4B (84~91), P4C (92~99) - where P4C's Pin99 is reused as EXTTRG

The remaining pins are GND (25, 50, 75, 100).

Jumper configuration and power on status

PCIe-7396 supports setting the default output level of each port independently through jumper wires (applicable to the moment of power on or uninitialized phase):

JA1~JA4: corresponding to ports A of PPI1~PPI4 respectively

JB1~JB4: corresponding to ports B of PPI1~PPI4 respectively

JC1~JC4: corresponding to ports C of PPI1~PPI4 respectively

Each jumper provides three modes (taking JA1 as an example):

1-2 Short circuit: The port is powered on to a low level (default)

2-3 Short circuit: When the port is powered on, it is at a high level

Jumper cap removed: port in high impedance state (floating)

This function is particularly important when driving external relays or LED indicator lights - to avoid momentary misoperation when powered on, it is recommended to set the safety level according to the load type.

Register programming and port control

The register mapping of PCIe-7396 (relative to the base address BASE) is divided into three categories: PPI data/control registers, interrupt control registers, and timing/counter registers.

4.1 PPI Digital Data Register (BASE+0x00, 0x10, 0x20, 0x30)

The 24 bit I/O data of each PPI is accessed through three 8-bit registers (low address corresponds to port A,+1 corresponds to port B,+2 corresponds to port C). Writing data sets the output, while reading data reads the current level (supports output state readback).

4.2 PPI Control Register (BASE+0x04, 0x14, 0x24, 0x34)

Write only, used to configure port direction. The control bits for each port (bits 0-2 correspond to ports A, B, and C respectively): write 1 as the output and write 0 as the input. Other positions are reserved.

4.3 External trigger control register (BASE+0x08/0x18/0x28/0x38 enabled, 0x0C/0x1C/0x2C/0x3C disabled)

After writing any value to the enable register, the data from ports A, B, and C corresponding to PPI will be simultaneously latched and read at the edge (programmable rising or falling edge) of the EXTTRG pin. This function can achieve synchronous acquisition of multiple input signals, suitable for encoder state latch or simultaneous sampling of multiple switches.

4.4 Change State (COS) Interrupt Control Register (BASE+0x60, 0x64, 0x68, 0x6C)

Corresponding to PPI1~PPI4 respectively, each port can independently enable COS detection. When the enabled channel experiences a level jump (rising or falling edge), INT1 (COS of PPI1/PPI2) or INT2 (COS of PPI3/PPI4) is triggered. The COS detection circuit continuously monitors all input channels and is very suitable for monitoring discrete events such as emergency stop buttons and limit switches.

Interrupt system configuration

Although the dual interrupt system of PCIe-7396 only occupies one PCIe interrupt, it can generate two independent interrupt requests (INT1 and INT2) through an internal multiplexer, and the software needs to distinguish the source through the interrupt service program.

5.1 Interrupt Source Control Register (ISC, BASE+0x50)

This register (write only) uses 4 bits (C1_1/C1-0 and C2_1/C2-0) to select the sources of INT1 and INT2 respectively:

Mode C1_1/C1-0 INT1 source trigger condition

0 00 COS P1&P2 (48 bits) any channel level change

1 01 P1C0 or P1C3 (logical combination) see Table 4-2

2 10 P1C0 falling edge triggered separately by falling edge

3 11 Event Counter (Counter # 0) Counter decreases to 0

INT2 is similar, with optional COS P3&P4, P2C0 combinational logic, P2C0 falling edge, or 32-bit timer interrupt.

5.2 Clear Interrupt Register (BASE+0x54)

Writing any value can clear the current interrupt request, which must be called at the end of ISR, otherwise it cannot respond to subsequent interrupts.

5.3 Edge combination triggering mode

When INT1 selects Mode 1 (P1C0 OR P1C3), the triggering condition is determined by the combination of two pin levels (see Table 4-2 in the manual):

P1C0=H and P1C3=X → Interrupt prohibited

P1C0=X and P1C3=L → Interrupt prohibited

P1C0=L and P1C3 falling edge → triggered

P1C0 rising edge and P1C3=H → trigger

This combination logic can generate complex conditional interrupts and is suitable for multi condition interlock protection.

Application of 8254 timer/counter

The onboard 8254 chip provides three 16 bit counters (Counter # 0~# 2) with a fundamental frequency of 2MHz.

Counter # 0: Event counter, input Pin 51 (EVENT), programmable edge triggered, event interrupt triggered when count drops to 0 (INT1 mode 3).

Counter # 1 and # 2: Cascade to form a 32-bit timer, which outputs as a timed interrupt (INT2 mode 4). The timing range can cover several microseconds to tens of minutes, and is set through the _7396_Cascaded_Timer API.

Typical applications:

Use timer interrupts to implement periodic I/O scans (such as reading 96 input states every 100ms).

Use an event counter to count the number of external pulses (such as flow meter or encoder signals) and trigger an interrupt when the preset value is reached.

Software drivers and development support

ADLINK provides MAPS series software packages:

MAPS Core: Includes Windows device drivers and ACE (ADLINK Connection Explorer) management tools for device discovery, resource allocation, and software panel debugging.

MAPS/C: C/C++development package, including header files, function libraries, and APIs, such as _7396_ DIO_WritePort、_7396_DIO_ReadPort、_7396_Set_Event_Edge、_7396_Cascaded_Timer、_7396_CLR_IRQ  Wait.

MAPS/LV: LabVIEW support library, including VI and sample programs.

Users do not need to manipulate the underlying registers and can quickly develop by calling the API directly. The latest version of the driver package can be downloaded from the ADLINK official website.

Terminal board selection

The SCSI connector of PCIe-7396 can be directly connected to the following terminal boards:

DIN-100S: Direct connection screw terminal board, no isolation, suitable for low-noise environments.

DIN-96DI: 96 channel optocoupler isolation input board, effectively suppressing grounding loops and protecting the host.

DIN-96DO (EOL): 96 channel optocoupler isolation output board, suitable for driving external relays or solenoid valves.

Choosing between isolated or non isolated solutions based on the type of on-site signal can significantly improve system reliability.

Common troubleshooting checklist

Possible causes and solutions for the phenomenon

The device is not recognized by the system due to poor PCIe slot contact or driver not installed. Replace the slot and reinstall the MAPS Core driver

The output cannot drive the load. If the current exceeds 48mA or the pulling current is insufficient, check the load current and add a transistor or relay if necessary

Input read error signal level is not within TTL range or not common ground. Ensure high level>2V, low level<0.8V, connect GND

External trigger invalid EXTTRG edge polarity setting error call _7396_Set-Event-Edge setting rising/falling edge

COS interrupt does not trigger port not configured as input or COS not enabled to check control register direction bit and COS control register

Timer interrupt frequency inaccurate 8254. Basic frequency or count value setting error. Reset through API, refer to 2MHz reference frequency

After the interrupt response, the system suspends the ISR. If the interrupt is not cleared, write the Clear Interrupt register at the end of the ISR

Multiple card interrupt conflicts do not distinguish between card IDs or interrupt sharing usage. Get actual IRQ and distinguish source