ADLINK cPCI/PCI-8554/R: A Complete Guide from Architecture to Application

ADLINK cPCI/PCI-8554/R: A Complete Guide from Architecture to Application

In the fields of industrial automation, data acquisition, and testing measurement, multifunctional counters/timer cards play a crucial role. They are not only the cornerstone of event counting, frequency measurement, and pulse width capture, but also the key components for building complex measurement and control systems. The cPCI/PCI-8554/R series multifunctional counter/timer card launched by ADLINK Technology occupies a place in many industrial applications with its flexible architecture, powerful feature set, and reliable PCI/CompactPCI interface. This article aims to deeply analyze the hardware architecture, core configuration, key application modes, and software development points of this series of boards, providing engineers with a detailed guide from theory to practice.

Hardware Architecture Overview: The Powerful Combination of Four Core 8254

The core competitiveness of cPCI/PCI-8554/R comes from its onboard four 8254 programmable interval timer/counter chips. 8254 is an industry standard counter chip, which contains three independent 16 bit subtraction counters inside each chip. Four chips work together to provide users with a total of 12 counters (numbered 1 to 12).

These 12 counters are not simply connected in parallel, but have achieved highly flexible interconnection through careful hardware design and software configuration. The flexibility of its architecture is mainly reflected in the following aspects:

Counter type classification: Counter 1 to 10 are designed as "independent counters". This means that their clock sources and gate signals can be independently configured through software, with diverse sources. Counter 11 and 12 are defaulted to be "cascaded counters", where the output of counter 11 (COUP11) serves as the clock input of counter 12, forming a 32-bit cascaded structure, mainly used in situations where large frequency division coefficients or long timing are required. Of course, users can also change counters 11 and 12 to independent mode through onboard jumpers (JP12, JP13), allowing their clock sources to choose between internal 8MHz or external inputs (ECLK11, ECLK12).

Flexible clock system: The clock source (CLKn) of each independent counter (1-10) can be freely switched among four sources through software:

External clock source (ECLKn): An external TTL signal from a connector, suitable for synchronizing with external events.

Front stage counter output (COUPn-1): Implement cascading between counters to build 32-bit, 48 bit, or even higher resolution counter chains.

Internal clock CK1: A programmable internal clock signal that can be divided by an 8MHz fundamental frequency or the output of counter 11 (COUP11), providing additional flexibility.

Counter 10 output (COUP10): Provides a clock option for feedback from a specific counter.

Intelligent gate control and debounce: The gate control signal (GATEn) of each independent counter (1-10) can be selected as internal default enable (high level) or external signal from the connector (ExtG n). External gating is the foundation for applications such as pulse width measurement and frequency measurement. Of particular importance, the board provides optional debounce circuits for external input clocks (ECLK 1-10) and external interrupt signals (E_INT). By using onboard jumpers (JP1~JP11) and software configuration (selecting the debounce clock DB_CK), common signal jitter and spike pulses in industrial sites can be effectively filtered out, ensuring measurement accuracy and system stability. The debounce principle requires the signal to maintain a stable state for at least four DB_CK cycles in order to be recognized as an effective level change.

Dual Interrupt System: This board supports dual interrupt sources, namely the output of counter 12 (COUP12) and external interrupt input (E_INT). These two interrupt sources share an interrupt number (INT A) on the PCI bus, but can be distinguished by software querying the status register (reading _8554_Get_iRQ_Status). This design is highly suitable for complex applications that require handling both periodic timed tasks (such as watchdog) and external emergency events simultaneously.

Digital I/O and power output: In addition to powerful timing/counting functions, the board also provides 8 TTL compatible digital inputs and 8 digital outputs for basic status monitoring and control. In addition, through the 100 pin SCSI-II connector, the board also provides+12V and+5V power outputs (with a current limit of 500mA per circuit), which can directly supply power to external sensors or low-power circuits, simplifying system design.

Detailed explanation of core configuration and jumper settings

The correct configuration is a prerequisite for the stable operation of the board. The configuration method of cPCI/PCI-8554/R combines hardware jumpers and software programming.

Hardware jumpers (JP1~JP15):

JP1~JP11: Enable the debounce function corresponding to external clocks ECLK1~ECLK10 and external interrupt E_INT, respectively. When the jumper is set to 1-2 (Enable), enable debounce; When set to 2-3 (Bypass), the bypass debounce circuit is used and the signal passes directly through. The default factory setting is bypass (without debounce function).