ADLINK cPCI/PCI-8554/R: A Complete Guide from Architecture to Application

JP12: Select the clock source for counter 11. When set to 1-2, select the external clock ECLK11; When set to 2-3 (default), select the internal 8MHz clock.

JP13: Select the clock source for counter 12. When set to 1-2, select the external clock ECLK12; When set to 2-3 (default), select the output COUP11 of counter 11.

JP14, JP15 (only cPCI-8554/R): Used to select the voltage source for the gate control signals (GATE11, GATE12) of counter 11 and counter 12, connected by default to VCC (high-level enable).

Software configuration (key API functions):

_8554Initialize: The card initialization function must be called first. It is responsible for obtaining the base address and interrupt number allocated by the PCI BIOS, and returning the number of cards present in the system.

_8554_SET_cntCLK: Select clock sources (ECLKn, COUPn-1, CK1, COUP10) for counters 1-10.

_8554_SET-CK1: Configure the source of the internal clock CK1 (8MHz baseband or COUP11).

_8554_SET-DBCLK: Configure the sampling clock DB_CK (COUP11 or 2MHz) for the debounce circuit. Note that the DB_CK frequency cannot exceed 2MHz.

_8554-Write_Counter: Write the count value to the specified counter and set its working mode (modes 0-5, corresponding to the six working modes of 8254, such as mode 2 as a frequency divider and mode 3 as a square wave generator).

_8554_Set-INT_Control: Independently enable or disable two interrupt sources (INT1 from COUP12, INT2 from E_INT).

Typical application scenarios and case analysis

This chapter will combine examples from the manual to deeply analyze several typical engineering applications, helping engineers quickly get started.

1. High precision frequency generator

Requirement: Generate an accurate, low-frequency square wave signal, such as a pulse with a period of 1 hour.

Challenge: A single 16 bit counter has a minimum output frequency of 8MHz/65536 ≈ 122Hz at an 8MHz clock, which is much higher than 0.000278Hz (1/3600).

Solution: Adopt counter cascading. In the manual example DEMO2, cascade counters 1, 2, and 3 together. Set the clock of counter 1 to internal 8MHz and the count value to 4000; The clock of counter 2 comes from COUP1, and the count value is set to 2000; The clock of counter 3 comes from COUP2, and the count value is set to 3600.

Total frequency calculation: 8000000/4000/2000/3600=1/3600 Hz. That is, COUP3 generates a pulse every 3600 seconds (1 hour).

Implementation points: In the software, it is necessary to first set the clock source of counter 2 to COUP1 and the clock source of counter 3 to COUP2 through _8554_SET-cntCLK. Then call _8554_Srite_Counter separately to set the mode and initial value of each counter (usually using mode 2 or mode 3). Gate control signal suspended (internal pull-up enabled).

2. Pulse width measurement

Requirement: Accurately measure the duration of high or low levels of an external TTL signal.

Principle: Use the gate control signal GATE to enable the counter. During the validity period of GATE, the counter counts the internal clock of a known frequency, and the pulse width is obtained by multiplying the count value by the clock period.

Solution: Taking manual DEMO3 as an example, connect the test signal to GATE1. Select an internal 2MHz clock as the clock source for counter 1. This clock can be obtained by dividing the internal 8MHz frequency by counter 2 (for example, counter 2 is set to divide by 4). At this time, the counting range of the counter is 1/2MHz=500ns, and the maximum measurable pulse width is 500ns * 65535 ≈ 32.8ms.

Implementation points: Configure counter 2 to be in frequency divider mode, generate a 2MHz clock, and use it as the clock source for counter 1 (via _8554_SET_cntCLK). Configure counter 1 as mode 0 (end of count interrupt) or mode 2 (frequency divider), with its gate source being external GATE1. When GATE1 is high, the counter starts counting; When GATE1 goes low, the counter stops. The software reads the current count value of counter 1 (_8554_ Read_Sunter), and then subtracts the current value from the initial value to obtain the count during the high-level period.

3. Frequency measurement

Requirement: Measure the frequency of an external TTL signal ranging from 1KHz to 100KHz.

Principle: The "frequency measurement method" is used, which measures the number of rising edges of the signal to be measured within a known precise time interval (gate time). Frequency=count value/gate time.

Solution: Two counters are required. A counter (such as counter 3) is used to generate accurate gate time, and its output serves as the gate signal for another counter (such as counter 1). As shown in manual DEMO4, use a cascaded or independent counter to generate a gate signal with a low pulse width of less than 0.65 seconds (ensuring that counter 1 does not overflow at a maximum frequency of 100KHz). Connect the test signal to the external clock ECLK1 of counter 1 and suggest enabling the debounce function. Counter 1 counts the rising edge of ECLK1 during the validity period of the gate signal.

Key points of implementation: Counter 3 operates in monostable or square wave mode, generating a negative pulse with precise width as GATE1. The clock source of counter 1 is set to ECLK1, and the gate source is set to external GATE1. After the gate signal ends, the software reads the count value of counter 1 and calculates the frequency to be measured based on the gate time.