ADLINK PCIe-7396 Digital I/O Card Deployment Guide

4.3 External trigger control register (BASE+0x08/0x18/0x28/0x38 enabled, 0x0C/0x1C/0x2C/0x3C disabled)

After writing any value to the enable register, the data from ports A, B, and C corresponding to PPI will be simultaneously latched and read at the edge (programmable rising or falling edge) of the EXTTRG pin. This function can achieve synchronous acquisition of multiple input signals, suitable for encoder state latch or simultaneous sampling of multiple switches.

4.4 Change State (COS) Interrupt Control Register (BASE+0x60, 0x64, 0x68, 0x6C)

Corresponding to PPI1~PPI4 respectively, each port can independently enable COS detection. When the enabled channel experiences a level jump (rising or falling edge), INT1 (COS of PPI1/PPI2) or INT2 (COS of PPI3/PPI4) is triggered. The COS detection circuit continuously monitors all input channels and is very suitable for monitoring discrete events such as emergency stop buttons and limit switches.

Interrupt system configuration

Although the dual interrupt system of PCIe-7396 only occupies one PCIe interrupt, it can generate two independent interrupt requests (INT1 and INT2) through an internal multiplexer, and the software needs to distinguish the source through the interrupt service program.

5.1 Interrupt Source Control Register (ISC, BASE+0x50)

This register (write only) uses 4 bits (C1_1/C1-0 and C2_1/C2-0) to select the sources of INT1 and INT2 respectively:

Mode C1_1/C1-0 INT1 source trigger condition

0 00 COS P1&P2 (48 bits) any channel level change

1 01 P1C0 or P1C3 (logical combination) see Table 4-2

2 10 P1C0 falling edge triggered separately by falling edge

3 11 Event Counter (Counter # 0) Counter decreases to 0

INT2 is similar, with optional COS P3&P4, P2C0 combinational logic, P2C0 falling edge, or 32-bit timer interrupt.

5.2 Clear Interrupt Register (BASE+0x54)

Writing any value can clear the current interrupt request, which must be called at the end of ISR, otherwise it cannot respond to subsequent interrupts.

5.3 Edge combination triggering mode

When INT1 selects Mode 1 (P1C0 OR P1C3), the triggering condition is determined by the combination of two pin levels (see Table 4-2 in the manual):

P1C0=H and P1C3=X → Interrupt prohibited

P1C0=X and P1C3=L → Interrupt prohibited

P1C0=L and P1C3 falling edge → triggered

P1C0 rising edge and P1C3=H → trigger

This combination logic can generate complex conditional interrupts and is suitable for multi condition interlock protection.

Application of 8254 timer/counter

The onboard 8254 chip provides three 16 bit counters (Counter # 0~# 2) with a fundamental frequency of 2MHz.

Counter # 0: Event counter, input Pin 51 (EVENT), programmable edge triggered, event interrupt triggered when count drops to 0 (INT1 mode 3).

Counter # 1 and # 2: Cascade to form a 32-bit timer, which outputs as a timed interrupt (INT2 mode 4). The timing range can cover several microseconds to tens of minutes, and is set through the _7396_Cascaded_Timer API.

Typical applications:

Use timer interrupts to implement periodic I/O scans (such as reading 96 input states every 100ms).

Use an event counter to count the number of external pulses (such as flow meter or encoder signals) and trigger an interrupt when the preset value is reached.

Software drivers and development support

ADLINK provides MAPS series software packages:

MAPS Core: Includes Windows device drivers and ACE (ADLINK Connection Explorer) management tools for device discovery, resource allocation, and software panel debugging.

MAPS/C: C/C++development package, including header files, function libraries, and APIs, such as _7396_ DIO_WritePort、_7396_DIO_ReadPort、_7396_Set_Event_Edge、_7396_Cascaded_Timer、_7396_CLR_IRQ  Wait.

MAPS/LV: LabVIEW support library, including VI and sample programs.

Users do not need to manipulate the underlying registers and can quickly develop by calling the API directly. The latest version of the driver package can be downloaded from the ADLINK official website.

Terminal board selection

The SCSI connector of PCIe-7396 can be directly connected to the following terminal boards:

DIN-100S: Direct connection screw terminal board, no isolation, suitable for low-noise environments.

DIN-96DI: 96 channel optocoupler isolation input board, effectively suppressing grounding loops and protecting the host.

DIN-96DO (EOL): 96 channel optocoupler isolation output board, suitable for driving external relays or solenoid valves.

Choosing between isolated or non isolated solutions based on the type of on-site signal can significantly improve system reliability.

Common troubleshooting checklist

Possible causes and solutions for the phenomenon

The device is not recognized by the system due to poor PCIe slot contact or driver not installed. Replace the slot and reinstall the MAPS Core driver

The output cannot drive the load. If the current exceeds 48mA or the pulling current is insufficient, check the load current and add a transistor or relay if necessary

Input read error signal level is not within TTL range or not common ground. Ensure high level>2V, low level<0.8V, connect GND

External trigger invalid EXTTRG edge polarity setting error call _7396_Set-Event-Edge setting rising/falling edge