Allen Bradley PLC-5 Classic Controller Complete Guide

Adapter mode: PLC-5/12,/15,/25 can serve as slave stations, accepting remote I/O scans from upper level controllers (such as PLC-5/250 or PLC-3) and processing their local I/O. The adapter mode processor and the upper computer can exchange discrete data of 4 or 8 words, or exchange up to 64 words of data through block transfer.

Block transmission: used for data exchange between analog modules or intelligent modules. In adapter mode, the BTW of the adapter processor must respond to the BTR of the upper computer (and vice versa). In scanner mode, block transfer requests are queued, and each remote I/O scanning cycle completes a maximum of one block transfer per rack address. If the program scanning time is much longer than the remote I/O scanning cycle, multiple block transfers may be completed within each program scan.

Engineering Warning:

If the adapter mode processor uses half slot addressing and is located in a 16 slot rack, block transfer functionality cannot be used - because the I/O image of rack 3 is occupied by local I/O and cannot be used for block transfer communication.

At the end device of the remote I/O link, switch 1 of SW3 must be set to ON (terminal resistance). If there are certain special devices on the link (such as some frequency converter adapters), a 150 Ω terminal resistor may need to be used instead of the standard 82 Ω, but this will limit the number of link devices to 16 and reduce the maximum baud rate to 115.2kbps.

Program development and troubleshooting

5.1 Application of Sequential Function Diagram (SFC)

SFC is a powerful language for describing sequential control processes. Each step corresponds to a control task (associated with a program file), and each transition condition corresponds to a logical judgment. For processes with multiple branches, parallel paths, or complex state machines, SFC is more intuitive than pure ladder diagrams.

SFC Structure Selection Guide:

Independent machine status → Steps+Transition

Single sequence event chain → Simple path

Multi channel selection branch → Select branch (scan from left to right, execute the first true condition)

Parallel path → Simultaneous branching (up to 7 parallel paths)

SFC programming precautions: The chart can be reset using GOTO jumps, global subroutines, macros (compression steps), and SFR instructions. A processor can only have one main program file (which can be SFC or ladder diagram).

5.2 Data Table File Structure

The PLC-5 memory is divided into a data area and a program area. The data table file includes:

Output image file (O0) - fixed size (PLC-5/10/12/15 is 32 words,/25 is 32-64 words)

Input image file (I1) - Same as above

Status File (S2) - Fixed 32 Word

Binary file (B3) - maximum 1000 words

Timer (T4), counter (C5), control structure (R6), integer (N7) - default file number, up to 1000 structures

Floating point number (F8) - up to 1000 floating point words

ASCII (A) and BCD (D) files - file number 3-999

The address format supports logical addresses (such as N23:0), I/O mapping addresses (I: 017/17), indirect addresses (N [N7:6]: 0), index addresses (# N23:0, offset taken from S: 14), and symbolic addresses (programming software functionality).

5.3 Fault Handling Mechanism

When the PLC-5 processor detects a major fault, it will immediately interrupt the current program. If a fault program has been configured (file number specified in S: 29), the processor will execute the fault program once. If the fault program clears the fault (by resetting the fault bit in S: 11), the processor returns to the original program to continue execution; Otherwise, the processor enters a fault mode.

Main fault code example:

12-19: Instruction operand type error, missing operand

20-23: Indirect address element number too large/negative/accessing undefined file

30-32: Subroutine nesting too deep or invalid jump

34-36: Timer/counter negative value, PID set value exceeding limit

74-79: SFC file error, too many activation steps, file type error

Power on protection: Setting bit 1 of S: 26 can prevent the processor from running directly after power failure recovery, but instead scan the faulty program first, and let the faulty program decide whether to allow startup. If the fault program does not clear bit 5 of S: 11, the processor will enter fault mode after the fault program ends.

Remote rack fault recovery:

When a remote I/O rack fails, the processor sets global fault bits (the lower 8 bits of S: 7, S: 32, S: 34) and partial rack status words (integer files specified by S: 16). There are three types of recovery strategies:

User generated main fault: When a fault position is detected, execute JSR to jump to the fault program and execute orderly shutdown

Reset input image table: Use the rack disable bit to force the input image bit to a safe value

Fault area programming: Use MCR area to power off non holding outputs to prevent misoperation

Performance optimization and scan time calculation

6.1 Composition of System Throughput

Throughput refers to the total time it takes for the input signal to change to the corresponding output action, consisting of the following components:

Input module delay (depending on module type, typically 20ms)