GE VMIVME-5565 Ultra High Speed Fiber Reflective Memory (with Interrupt Function)

GE VMIVME-5565 Ultra High Speed Fiber Reflective Memory (with Interrupt Function)

Product Overview

VMIVME-5565 is a member of the VMIC Reflective Memory Real time Fiber Network product series based on VMEbus. It adopts a standard 6U European card shape and can be integrated with VMIMPC-5565 and VMIPCI-5565 of the same series into networks using standard fiber optic cables. Each card in the network is called a node. It enables computers, workstations, PLCs, and other embedded controllers with different architectures and operating systems to share data in real time, with convenient operation. Data is transmitted through written memory (SDRAM), and the onboard circuit automatically transfers the data to all other nodes, almost without the involvement of any host processor or system.

Core Features

A high-speed and easy-to-use fiber optic network with a serial rate of 2.12 Gbaud.

Supports up to 256 nodes.

When using multimode fiber, the connection distance can reach 300 meters, and single-mode fiber can reach 10 kilometers.

Dynamic packet size, with each packet containing 4 to 64 bytes of data.

The transmission rate varies depending on the packet size, with 43 Mbytes/sec for 4-byte packets and 174 Mbytes/sec for 64 byte packets.

Up to 128 Mbyte of SDRAM reflective memory with parity check.

Supports VMEbus DMA.

Four universal network interrupts, each with 32-bit data.

Equipped with error detection function.

Standardize compliance

Compliant with the VMEbus specification (ANSI/IEEE STD 1014-1987, IEC 821 and 297), with the relevant mnemonics A32: A24; D32/D16/D08 (EO): Slave: 39/3D:09/0D。

Working principle

Basic operation: Each node in the network is interconnected in a daisy chain loop through fiber optic cables. The data transmission is initiated by the VMEbus host system writing to the onboard SDRAM. During the writing process, the onboard circuit automatically writes the data and related information into the transmit FIFO, which then forms variable length data packets ranging from 4 to 64 bytes. These packets are transmitted through the fiber optic interface to the receiver of the next board. After receiving, the relevant circuit opens the data packet and stores it in the receiving FIFO, then writes it to the corresponding position of the local onboard SDRAM, and routes the data to its own sending FIFO. This process is repeated until the data returns to the source node and is removed.

Front panel LED indicator lights: There are three LED indicator lights, with the bottom red being the status indicator light. When powered on, it defaults to "ON" and the status can be switched by writing to bit 31 of the control and status registers; The yellow color in the middle is the signal detection indicator light, which is "ON" when the receiver detects light; The green light at the top is the self data indicator light, which is "ON" when detecting the return of self data.

Register group: including Universe II registers (specific control and status and DMA control registers located in the VMEbus bridge, byte order in small end mode) and Reflective Memory (RFM) control and status registers (implementing unique features of the 5565 series reflective memory board).

Reflective memory RAM: available in two sizes of 64 Mbytes or 128 Mbytes, with parity check function. The parity check function is not enabled when powered on and needs to be enabled through a specific bit setting. When enabled, only 32-bit or 64 bit writes are allowed.

Interrupt circuit: There is a programmable VMEbus interrupt output, and the interrupt source can be separately enabled and monitored through the local interrupt status register (LISR) and local interrupt enable register (LIER).

Network Interruption: capable of transmitting interrupt packets on the network, which can be directed to specific nodes or broadcasted to all nodes, including sender node ID, destination node ID, interrupt type information, and 32-bit user-defined data. The receiving node will store the relevant information in the corresponding FIFO.

Redundant transmission mode: configured through jumper E5, each data packet is transmitted twice in redundant mode, and the receiving node evaluates the transmission situation. Although this mode reduces the probability of data loss, it will lower the effective network transmission rate.

Abnormal packet removal operation: Abnormal packets refer to packets that do not belong to any node in the network. VMIVME-5565 can work as one of the two abnormal master nodes. When an abnormal packet is detected, it will be removed from the ring and relevant flag bits will be set.

Byte order: Due to the tradition of different microprocessor manufacturers, there is a distinction between big endian and small endian. The PCI to VMEbus interface of VMIVME-5565 uses Intel or equivalent bridge chips, adopts small endian byte order, and the interface has external byte order conversion logic, which can achieve independent master/slave hardware byte order conversion.

Configuration and Installation

Unpacking program: Components may be sensitive to electrostatic discharge, so attention should be paid when handling them. After unpacking, check for any damage.

Switch/jumper configuration and position

Node ID Switch (S6): An 8-bit switch that sets the node ID within the range of 0 to 255. Each node ID must be unique, and the switch position "ON" corresponds to 0, while "OFF" corresponds to 1.

Jumper E5 (redundant mode configuration): Used to configure redundant or non redundant transmission modes and select abnormal master nodes, with different pin hopping states corresponding to different functions.

Register and memory configuration switch: VMIVME-5565 occupies two independent address spaces on VMEbus. The control and status register spaces can be set as extended address space (A32) or standard address space (A24), and the SDRAM memory space can be set as extended address space (A32). When configuring, address overlap should be avoided. The switch "ON" corresponds to address bit 0, and "OFF" corresponds to address bit 1.

Physical installation: Power off installation, ensure correct switch settings, fix after installation on the chassis, and connect fiber optic cables according to the ring topology.

Front panel description: Optical transceiver, "RX" for receiver, "TX" for transmitter, using "LC" type fiber optic cable, with three LED indicator lights as described earlier. When operating, pay attention to dust prevention and avoid looking directly at the transmitter.

Cable configuration: There are multi-mode or single mode fiber optic interfaces, and cables and connectors have specific specifications.

Connectivity: Nodes are connected in a circular manner.

Programming

RFM Control and Status Register: Located at a specific offset address, it includes local control and status registers, local interrupt status registers, local interrupt enable registers, etc. Each register has different functions and bit definitions.

RFM network registers: including Network Target Data Register (NTD), Network Target Node Register (NTN), Network Interrupt Command Register (NIC), as well as various interrupt sender IDs and data FIFOs, used for generating and receiving network interrupts.

Example of network interrupt handling: including the steps for setting interrupt programs and serving network interrupts.

Universe II registers: divided into Universe II control and status registers and Universe II DMA registers, each with different offset addresses, functions, and bit definitions, which can be used to control and monitor interrupts and DMA transfers.

DMA source and destination addresses: determined by specific registers, transfer direction determined by L2V bits, alignment requirements for addresses, adjustable transfer size and data width, DMA command packet pointer pointing to command packet, DMA startup, VMEbus ownership, completion, and termination all have corresponding operations and mechanisms.