Microchip dsPIC30F High Performance 16 Bit Digital Signal Controller Field Application and Troubleshooting Guide

Watchdog Timer (WDT): default enabled (factory configuration word WDTEN=1). If the CLRWDT instruction is not executed in a timely manner in the main loop, a reset will be triggered after a few milliseconds. During the development phase, it is recommended to disable WDT in the configuration word or control it through the _SWDTEN software.

Reason identification for reset: Read the RCON register (reset control register), where bits such as BOR, WDTO, EXTR can indicate the last reset source. Saving this value during firmware startup and outputting it through the communication port greatly facilitates remote fault diagnosis.

Chapter 2 Troubleshooting of Advanced Analog Peripherals

2.1 10 bit/12 bit ADC module

The dsPIC30F offers two types of ADCs: a 500 ksps 10 bit ADC and a 100 ksps 12 bit ADC, both of which support up to 16 channels, differential input, and multi-channel sample and hold. Common ADC faults on site include conversion value jumping, excessive deviation, or complete non conversion.

Problem 1: The ADC conversion result always remains 0 or at full scale

Possible reasons:

The ADC module is not properly enabled (ADON bit is 0)

Insufficient sampling time (SAMC bit set too small, internal capacitor not charged to input voltage)

Reference voltage configuration error (VCFG bit selected non-existent pin)

Troubleshooting process:

Check ADCONx register: ADON=1, ADFM result alignment meets expectations.

Increase sampling time: for example, changing SAMC from 3TAD to 31TAD, or using automatic sampling triggering.

If using external Vref+and Vref - pins, ensure that the circuit board is connected to the correct voltage (not suspended).

Single step debugging: Write ADCON1bits. SAMP=1 to start sampling, delay, then set SAMP=0 to start conversion, and observe the DONE bit.

Problem 2: Nonlinear or noisy conversion results

Reason:

There is high-frequency digital signal (such as PWM, SPI clock) crosstalk near the analog input pins.

Internal Vref is unstable.

The ADC clock is higher than the recommended value (the maximum ADCLK of a 10 bit ADC is about 5MHz).

Solution:

Separate analog and digital ground on PCB and connect them at a single point.

Add RC low-pass filtering (R=1k Ω, C=0.1μF）。

Place the CPU in SLEEP or IDLE mode during conversion to reduce digital noise (ADC can operate in sleep mode).

Using oversampling and averaging techniques: taking the average after 8 consecutive conversions to effectively improve resolution.

2.2 Low Voltage Detection (LVD)

The LVD module allows software to set a voltage trigger point (internal reference voltage) that generates an interrupt (priority 7, non maskable) when VDD is below a threshold. This is crucial for applications that require saving critical data before power outages. Common false triggering problems are usually caused by excessive power ripple or setting thresholds too close to the operating voltage. It is recommended to set a hysteresis window of at least 0.2V and add digital filtering (responding after detecting low voltage twice in a row) to the interrupt service routine.

Chapter 3 On site Debugging of Motor Control Peripherals

3.1 Pulse Width Modulation (PWM) Module

The PWM module of dsPIC30F is the core of motor control, supporting up to 8 PWM outputs (4 duty cycle generators), 16 bit resolution, edge alignment or center alignment mode, and has a "special event trigger" function for synchronous ADC sampling.

Typical fault: PWM has no output or abnormal waveform

PWM module not enabled: Check if PTCONbits.PTEN is set to 1.

Pin reuse conflict: PWM pins may be configured as general-purpose I/O or other peripherals. It is necessary to correctly set the PWM function in registers such as TRISx and OCxx.

Dead time incorrect setting: In complementary mode, if the dead time register DTCON1 is set too large, it may cause the effective pulse width to be zero. The oscilloscope observation should show a clear dead zone between the upper and lower bridge arms, but there are still pulses.

Fault pin (FLTX) activation: If fault protection (FLTACON) is enabled, the external fault signal will force the PWM output to a safe state (high resistance or low level). Check the FLTACON register and fault input pin levels.

Dual update in center aligned mode: In center aligned PWM, the duty cycle can be updated at the beginning and midpoint of the cycle to improve control bandwidth. If PTMOD and PTCON are not configured correctly, it may cause update delays or waveform asymmetry.

3.2 Orthogonal Encoder Interface (QEI)

The QEI module is used to read the A, B, and Z phase signals of the incremental encoder, providing a 16 bit position counter, supporting x 2 and x 4 modes, and built-in digital filtering.

common problem:

Counter not counting or direction error: Check if encoder A and B phases are connected in reverse (swapping wiring can solve the problem); Confirm that the QEIEN bit in QEICON is 1; Is the sampling clock of the digital filter set too high to filter out effective pulses.

Position jump: It is often caused by interference with the encoder signal. Use differential encoders (such as RS-422) and twisted shielded wires on the PCB, while enabling the Schmitt trigger for QEI input.