Performance characteristic analysis
1. Memory access performance
DRAM access: At 25 MHz, non interleaved reads have 4-2-2-2 cycles, while interleaved reads can be increased to 4-1-1-1.
Flash/EPROM access: programmable for 3-10 clock cycles per byte.
DMA transfer: SCSI DMA supports a bandwidth of 44 MB/s, while Ethernet DMA supports a bandwidth of 20 MB/s.
2. Real time and reliability
Watchdog timer: Both MCchip and VMEchip2 integrate a watchdog, which can trigger a system reset or local reset upon timeout.
Local bus timeout: Programmable timeout period (8 µ s to 256 µ s) to prevent bus suspension.
Battery backup system: SRAM and real-time clock are backed up by lithium batteries, with data retention time exceeding 2 years.
3. Scalability and compatibility
Support VMEbus Rev. C1 standard
Compatible with Industry Pack Rev 1.0 specification
Provide a complete driver and debugging toolchain
Application scenarios and system integration suggestions
MVME162 is suitable for the following fields:
Industrial control: real-time data acquisition, motion control, process monitoring
Communication system: protocol conversion, gateway devices, base station control
Experimental testing: Hardware in the loop simulation, data recording, instrument control
Embedded development: customized hardware platform, prototype verification
System integration precautions:
If using the EIA-530 interface, avoid mixing it with the MVME712 transition module as it does not support balanced signals.
In a multiprocessor system, it is necessary to allocate VME interrupts and bus bandwidth reasonably.
In high temperature environments, it is necessary to ensure that the heat dissipation ducts are unobstructed, and low-power IP modules are preferred.
To obtain FCC Class A certification, all external cables must be shielded and grounded.
