NI CompactRIO Embedded System

Main clock source selection:

The onboard clock frequency is 12.8 MHz or 13.1072 MHz, depending on the module type (e.g. NI 9225 uses 12.8 MHz, NI 9218 uses 13.1072 MHz).

When synchronizing multiple modules of different models, the maximum sampling rate is limited by the main clock frequency. For example, if NI 9225 (12.8 MHz internal frequency division) is used as the master clock and NI 9218 (13.1072 MHz) is used as the slave, the maximum sampling rate of the slave will be limited to 50 kS/s (instead of its original 51.2 kS/s).

Trigger delay calculation:

For delta sigma modules (such as NI 9231), the first sampling delay formula is (281.625 * m * n+5.5) * Tmaster, where m is the sampling rate, n is the clock division, and Tmaster is the main clock cycle. When designing FPGA programs, sufficient time should be reserved before the start of the loop, otherwise the first data point will be lost.

Scan clock synchronization:

Use the Scan Clock I/O option to monitor when the scanning engine is transmitting data. By using the Wait on Rising Edge method, it is possible to ensure that reading and writing user-defined I/O variables do not conflict with the scanning engine and avoid data inconsistency.