ADLINK ACL-8112 Data Acquisition Card Configuration and Programming

ADLINK ACL-8112 Series Multifunctional Data Acquisition Card Configuration and Programming Complete Guide

In the fields of industrial automation testing, laboratory research, and process control, multifunctional data acquisition cards (DAQs) are the core bridge connecting the analog/digital world with computer systems. The ADLINK ACL-8112 series, as a classic ISA bus multifunctional data acquisition card, has long served the upgrading of old production lines, teaching experiments, and specialized testing equipment with a 100kHz sampling rate, 12 bit resolution, 16 analog inputs, 2 analog outputs, 16 digital I/O, and programmable counters/timers. Although ISA bus has gradually been replaced by PCI/PCIe, a large number of existing systems still rely on this series of cards for stable operation. This article systematically outlines the complete engineering application points of ACL-8112 (including DG/HG/PG sub models) from hardware architecture, jumper configuration, signal connection, low-level register programming to calibration and maintenance, providing practical reference for maintenance and secondary development engineers.

Product family and selection differences

The ACL-8112 series includes three models, with the core difference being the gain configuration of the analog input front-end:

ACL-8112HG (High Gain Version): Built in programmable instrumentation amplifier, supporting 8 levels of gain including × 0.5, × 1, × 5, × 10, × 50, × 100, × 500, and × 1000. The minimum bipolar input range can reach ± 5mV, and the minimum unipolar range is 0-10mV. It is specifically designed for measuring weak signals such as thermocouples and strain gauges.

ACL-8112DG (low gain version): Supports five levels of gain, including x 0.5, x 1, x 2, x 4, and x 8, with a minimum polarity of ± 0.625V. It is suitable for general industrial sensors (such as voltage on 4-20mA current sampling resistors).

ACL-8112PG (Programmable Gain Edition): Supports five levels of gain, including * 1, * 2, * 4, * 8, and * 16. The input range can be selected as ± 5V or ± 10V through hardware jumpers. The combination of gain and range provides multiple ranges from ± 10V to ± 0.3125V.

All models offer 16 single ended or 8-channel differential analog inputs (PG version only single ended), 2 12 bit D/A outputs, 16 TTL digital inputs and 16 digital outputs, as well as 1 independent 8254 timer/counter channel (the other two channels are cascaded as A/D sampling clocks).

Selection suggestion: HG version is preferred for weak signals (<100mV); Select DG or PG version for universal sensor signals (0~5V/0~10V); The PG version is more suitable for situations that require flexible switching of multiple gains, and its hardware jumpers can change the maximum input range as a whole (± 5V/± 10V).

Detailed explanation of hardware installation and jumper configuration

2.1 Base Address Setting (SW1)

ACL-8112 occupies 16 consecutive I/O addresses, and the base address is set within the range of 0x200~0x3FF through a 6-digit DIP switch (SW1), with a default of 0x220. Address line A9 is fixed at 1 (i.e. base address ≥ 0x200), A0~A3 are fixed at 0 (16 byte alignment), and users can adjust A8~A4 (corresponding to DIP1~DIP5) to change the address. For example, when set to 0x220, the binary address lines A9~A0 are 1 0 0 0 1 0 0 0 0 0, that is, DIP1~DIP5 are OFF ON OFF (according to the default image).

Attention: The base address must not conflict with PC built-in devices (such as COM/LPT ports) or other expansion cards. Common free addresses include 0x300, 0x310, etc. You can use MSD under DOS or Windows Device Manager to view occupied resources.

2.2 Analog input channel configuration (JP3, DG/HG only)

JP3 control input mode:

Single ended mode (default): All 16 channels are based on AGND as a reference, suitable for floating signal sources;

Differential mode: 8 differential channels (CHO~CH7), with positive and negative terminals connected to AI0~AI7 and AI8~AI15 respectively, suitable for grounding reference sources to suppress common mode noise.

The PG version is fixed at 16 single ended and does not have this jumper.

2.3 DMA channel selection (JP7/JP8)

A/D supports high-speed transmission in DMA mode, with the option to select DMA channel 1 or channel 3:

If the PC uses a floppy disk drive (occupying DMA2), it is recommended to choose DMA3;

If using a hard drive (usually not occupying DMA), it is optional, but DMA1 is recommended by default.

Refer to Figure 2.4 in the manual for jumper settings - simply place the short-circuit block in the corresponding "CH1" or "CH3" position.

2.4 Trigger Source Selection (JP4)

A/D conversion can be triggered by internal or external signals:

Internal trigger (default): further divided into software trigger and timer trigger (selected by mode control register);

External trigger: Input rising edge trigger through the 17 pin (ExtTrig) of CN3, suitable for synchronous sampling with external events.

2.5 Interrupt IRQ Setting (JP5)

Supports 9 levels including IRQ3, 5, 6, 7, 9, 10, 11, 12, and 15, with IRQ15 as the default. Insert the jumper cap into the corresponding numbered pin to select the interrupt. If using interrupt transfer mode, it is necessary to ensure that the IRQ is not occupied by other devices (such as IRQ3, which is usually used for COM2, and IRQ7, which is used for LPT1 and should be avoided).

2.6 D/A reference voltage setting

The output range of D/A is determined by the reference voltage (internal -5V or -10V, or external input):

Internal reference selection (JP2): further select -5V or -10V from JP1 (DG/HG) or JP8 (PG);

External reference: Connect from pin 31 (ExtRef1) and pin 12 (ExtRef2) of CN3 respectively, with a maximum voltage range of ± 10V (unipolar output 0~Vref).

Output calculation formula: Vout=- VRef × (DAn/4096). For example, when Vref=-10V, the digital quantity is 0 → 0V, 4095 →+9.9976V.

2.7 Timer Clock Source (JP6, DG/HG only)

The clock source for counter 0 can choose between an internal 2MHz or an external clock (via the 37 pin ExtCLK of CN3). Default internal 2MHz, suitable for frequency generator mode; An external clock can be used for event counting.

2.8 A/D input maximum range (JP9, PG version only)

The PG version sets the maximum input range to ± 5V or ± 10V through JP9, and combines it with the gain value (× 1~× 16) to determine the actual range (such as ± 0.625V for gain × 16 at ± 10V).

Definition of Signal Connections and Terminals

ACL-8112 provides three connectors:

CN1 (20 core IDC): Digital output channels DO0~DO15;

CN2 (20 core IDC): Digital input channels DI0~DI15;

CN3 (37 core D-Sub): Analog input/output, timer/counter, and external reference signal.

3.1 Key points of analog input wiring

Floating ground signal source (single ended mode): The positive end of the signal is connected to AIn, and the negative end is connected to AGND (see Figure 3.4). Multiple floating ground sources need to be shared.

Ground source (differential mode): The positive terminal of the signal is connected to AIn+, and the negative terminal is connected to AIn -, using a differential suppression ground loop (see Figure 3.5).

Differential source (differential mode): If the signal source itself is a differential output (not grounded), a short circuit should be added between the AGND and the negative terminal of the signal to avoid damage to the device due to high common mode voltage (see Figure 3.6).

Important: AGND is an analog ground and is connected to the digital ground (GND) at a single point inside the board. It cannot be short circuited externally to avoid introducing digital noise.

3.2 Analog Output

AO1 (30 pins) and AO2 (32 pins) output 0~Vref (unipolar) with a load capacity of ± 5mA. If a voltage based industrial standard (such as 0~10V) is required, an internal reference of -10V can be set.

3.3 Digital I/O

All DIOs are TTL compatible, with input high level ≥ 2.0V, low level ≤ 0.8V; output high level ≥ 2.4V (source current 0.4mA), low level ≤ 0.4V (sink current 8mA). It can directly drive 74LS series logic circuits or optocouplers.

3.4 Timer/Counter

CN3 provides CLK (pin 37), GATE (pin 36), and COUP0 (pin 35) for counter 0. CLK can be selected as an internal 2MHz or external input, GATE level controls counting enable, and COUP outputs pulse or level status.

Register programming model

The register mapping of ACL-8112 is the core of low-level programming. After setting the base address to BASE, the offset of each functional register is as follows:

Offset read operation and write operation

BASE+0 counter 0 current value counter 0 initial value

BASE+4 A/D low byte D/A channel 1 low byte

BASE+5 A/D high byte (including DRDY bit) D/A channel 1 high byte

BASE+6 DI low byte D/A channel 2 low byte

BASE+7 DI high byte D/A channel 2 high byte

BASE+8 Unused Interrupt Request

BASE+9 does not use A/D range control

BASE+10 Unused Channel Multi Channel Switch

BASE+11 unused mode control

BASE+12 not triggered by software A/D

BASE+13 Unused DO Low Byte

BASE+14 unused DO high byte

4.1 A/D Conversion Process

Write BASE+10 to select the channel (CL3~CL0 are channel numbers, when DG/HG is differential, set CS0/CS1 to 1 at the same time);

Write BASE+9 to set gain and polarity (see Tables 4.2-1 to 4.2-4);

Write BASE+11 selection mode (0=software trigger+polling, 2=timer+DMA, 6=timer+interrupt, etc.);

Trigger conversion:

Software mode: Write any value to BASE+12;

Timer mode: Set the initial value of counter 1/2 (BASE+1/BASE+2);

External mode: waiting for the rising edge of ExtTrig;

Read data: When polling the DRDY bit (bit4) of BASE+5 to 0, read BASE+4 (low 8 bits) first, then read BASE+5 (high 4 bits+DRDY), and the DRDY will be automatically cleared.

4.2 Timer Operation (8254)

Write control word into BASE+3 (format: SC1/SC0 select counter, RL1/RL0 select read/write mode, M2/M1/M0 select mode, BCD select binary/BCD);

Counter 0 is available for users to freely use (programmable as square wave generator, monostable, event counting, etc.);

Counter 1 and 2 are cascaded to form an A/D sampling clock with a frequency of 2MHz/(c1 × c2), where c1 and c2 are 16 bit initial values (1~65535). The maximum theoretical frequency is 500kHz, but due to the limitation of ADC conversion time, it is actually ≤ 100kHz.

C Language Library Function Programming Guide

ADLINK provides the Borland C/C++library (header file 8112. h) for DOS environment, with a total of 23 functions covering initialization DIO、DA、AD、 Timer operation and advanced DMA/interrupt transmission.

5.1 Initialization and Multi Card Switching

_8112Initial (card_number(), type, base_dedress): It must be called first, and the type parameter distinguishes versions (such as A8112BHG, A81122C-DG, etc.). Only two cards (CARD_1/CARD_2) are supported due to limited ISA DMA channels.

_811_2Switch_Card_no (card_number): In a multi card system, switch the current operating card, and subsequent functions apply to that card.

5.2 Simulated Input Functions

_811_2AD_Set_Channel (ch): Select the A/D channel (0-15 single ended, 0-7 differential).

_811_2AD_Set_Sange (range): Set the gain and polarity (such as AD_S_5_V, AD-U_10-V, etc., specific constants can be found in the manual table).

_8111_AD_Set_made (mode): Select the triggering and transmission mode (ADtmoDE_1 software triggering+polling, ADtmoDE-6 timer triggering+interrupt, etc.).

_811_2AD_Soft_Trig(): The software triggers a conversion once.

_811_2AD_Squire (&data): Polling waits for conversion to complete, returns 12 bit data.

_811_2AD_Timer (c1, c2): Set the timer frequency division coefficient, sampling rate=2MHz/(c1 * c2).

_8112AD_DMA_Start (ch, range, dma_ch, irq, count, buffer, c1, c2): Start the timer to trigger+DMA batch collection (running in the background), and allocate sufficient memory in advance.

_8112AD_DMA_Status (&status,&count): Check the DMA progress (whether it is completed and the number of points transferred).

_8112AD_DMA_Stop (&count): Stop DMA and return the actual number of transfer points.

Typical continuous collection code snippets:

_8112_Initial(CARD_1, A8112C_DG, 0x220);

_8112_AD_Set_Channel(0);

_8112_AD_Set_Range(AD_B_5_V);

_8112_AD_Timer(100, 10); //2MHz/(1000)=2kHz sampling rate

_8112_AD_DMA_Start(0, AD_B_5_V, DMA_CH_1, IRQ15, 4096, buffer, 100, 10);

while(1) {_8112_AD_DMA_Status(&status, &count);if(status) break;}

_8112_AD_DMA_Stop(&count);

5.3 Analog Output

_811_2DA (ch, data): Output 0~4095 to the specified DA channel (DA_C_1 or DA_C_2). Low byte data is written first, high byte data is written later (double buffering order has been processed internally in the library).

5.4 Digital I/O

_8111_DI (port,&data): Read low byte (DI_LO-BYTE) or high byte (DI-HI-BYTE).

_8111_DI_Channel (ch,&data): Read the status of the pointing position (0~15).

_8111_DO (port, data): Write low or high bytes to the DO port.

5.5 Timer User Mode

_8111_TIMER_Start (mode, c0): Start counter 0 (mode 0~5), clock source determined by hardware jumper.

_8111_TIMER_Read (&value): Read the current count value.

_8111_TIMER_Stop (&value): Stop the counter.

Calibration process and accuracy maintenance

It is recommended to perform calibration annually or after significant changes in ambient temperature. Required tools: 5 and a half digit digital voltmeter, precision voltage calibration source (or low-noise DC source), and accompanying 8112utilit.exe calibration program.

VR adjustment points (DG/HG version has 6, PG version has 5):

VR1: A/D Full Scale

VR2: A/D Bipolar Offset

VR3: D/A Channel 1 Full Scale

VR4: D/A Channel 2 Full Scale

VR5: PGA offset (reduces amplifier drift)

VR6: A/D unipolar offset (DG/HG only)

Bipolar calibration steps (taking ± 5V as an example):

Input -4.9987V to AI0 (for AGND), adjust VR2 to make the reading jump between 0 and 1;

Input+4.9963V, adjust VR1 to make the reading jump between 4094 and 4095;

Repeat checks and iterate if necessary.

Unipolar calibration (0~10V):

Input+1.22mV, adjust VR6 to make the reading jump between 0 and 1;

Input+9.9963V and adjust VR1 to make the reading jump between 4094 and 4095.

After calibration is completed, records should be saved and the calibration date should be marked in the application. If an external reference voltage is used, additional calibration of the reference source's own accuracy is required.

Common troubleshooting

Fault 1: The A/D reading is always 0 or at full scale

Check if the channel selection register is written correctly (BASE+10);

Confirm whether the polarity of the input signal is consistent with the setting (unipolar input negative voltage will cause truncation);

Check if JP3 matches the actual wiring mode (differential/single ended);

Measure the voltage between AGND and AI0 to confirm that the signal has indeed reached the board.

Fault 2: D/A has no output or fixed output

Check the D/A reference voltage setting (internal/external) and measure the voltage at the VR1/VR2 output terminals;

Confirm the double buffer write order (low first, high later), and if using library functions, there is no need to worry;

Check if the contact of pin CN3 is good (pin AO1 is 30, pin AO2 is 32).

Fault 3: DMA data transfer disorder or system crash

Confirm that the DMA channel is not occupied by other devices (such as disabling DMA3 for onboard LPT in BIOS);

Check if the buffer array is located in regular memory (<1MB) and has sufficient size (ISA DMA only supports low 16MB address space, use _fmalloc or malloc under DOS to ensure physical address continuity);

Confirm that the initial value product of the timer is ≥ 20 (i.e. sampling rate ≤ 100kHz), otherwise it may exceed the ADC capability.

Fault 4: Interrupt not triggered or service program not executed

Confirm that the IRQ jumper is consistent with the software settings (corresponding to BASE+11 mode);

Check if the interrupt service program is installed correctly and clear the interrupt (write any value to BASE+8);

Confirm that the interrupt vector is not occupied by BIOS or other drivers (run INT query).

Fault 5: Counter 0 cannot output the expected frequency

Check if the CLK jumper selects internal 2MHz;

The counting format (BCD/binary) in the control word should match the initial value (if binary counting is used, the initial value range is 0~65535; BCD is 0~9999);

Confirm that the GATE pin level is high (it may be pulled low if suspended).

Maintenance and upgrade suggestions

ISA slot gold finger should be cleaned regularly with an eraser to avoid oxidation and poor contact;

If the electrolytic capacitors on the board (especially the power filter capacitors) have been used for more than 10 years, it is recommended to replace them to prevent leakage and damage to the PCB;

For new projects, it is recommended to migrate to PCI/PCIe bus products (such as ADLINK PCI-9111/9113, etc.), but existing systems can still rely on ACL-8112 for stable service;

The driver program is included in the ADLINK CD (DOS library). If you need a Windows environment, you can purchase the ACLS-DLL2 development kit (supporting Win95/98/NT/2000).