ADLINK ACL-8112 Data Acquisition Card Configuration and Programming

ADLINK ACL-8112 Series Multifunctional Data Acquisition Card Configuration and Programming Complete Guide

In the fields of industrial automation testing, laboratory research, and process control, multifunctional data acquisition cards (DAQs) are the core bridge connecting the analog/digital world with computer systems. The ADLINK ACL-8112 series, as a classic ISA bus multifunctional data acquisition card, has long served the upgrading of old production lines, teaching experiments, and specialized testing equipment with a 100kHz sampling rate, 12 bit resolution, 16 analog inputs, 2 analog outputs, 16 digital I/O, and programmable counters/timers. Although ISA bus has gradually been replaced by PCI/PCIe, a large number of existing systems still rely on this series of cards for stable operation. This article systematically outlines the complete engineering application points of ACL-8112 (including DG/HG/PG sub models) from hardware architecture, jumper configuration, signal connection, low-level register programming to calibration and maintenance, providing practical reference for maintenance and secondary development engineers.

Product family and selection differences

The ACL-8112 series includes three models, with the core difference being the gain configuration of the analog input front-end:

ACL-8112HG (High Gain Version): Built in programmable instrumentation amplifier, supporting 8 levels of gain including × 0.5, × 1, × 5, × 10, × 50, × 100, × 500, and × 1000. The minimum bipolar input range can reach ± 5mV, and the minimum unipolar range is 0-10mV. It is specifically designed for measuring weak signals such as thermocouples and strain gauges.

ACL-8112DG (low gain version): Supports five levels of gain, including x 0.5, x 1, x 2, x 4, and x 8, with a minimum polarity of ± 0.625V. It is suitable for general industrial sensors (such as voltage on 4-20mA current sampling resistors).

ACL-8112PG (Programmable Gain Edition): Supports five levels of gain, including * 1, * 2, * 4, * 8, and * 16. The input range can be selected as ± 5V or ± 10V through hardware jumpers. The combination of gain and range provides multiple ranges from ± 10V to ± 0.3125V.

All models offer 16 single ended or 8-channel differential analog inputs (PG version only single ended), 2 12 bit D/A outputs, 16 TTL digital inputs and 16 digital outputs, as well as 1 independent 8254 timer/counter channel (the other two channels are cascaded as A/D sampling clocks).

Selection suggestion: HG version is preferred for weak signals (<100mV); Select DG or PG version for universal sensor signals (0~5V/0~10V); The PG version is more suitable for situations that require flexible switching of multiple gains, and its hardware jumpers can change the maximum input range as a whole (± 5V/± 10V).

Detailed explanation of hardware installation and jumper configuration

2.1 Base Address Setting (SW1)

ACL-8112 occupies 16 consecutive I/O addresses, and the base address is set within the range of 0x200~0x3FF through a 6-digit DIP switch (SW1), with a default of 0x220. Address line A9 is fixed at 1 (i.e. base address ≥ 0x200), A0~A3 are fixed at 0 (16 byte alignment), and users can adjust A8~A4 (corresponding to DIP1~DIP5) to change the address. For example, when set to 0x220, the binary address lines A9~A0 are 1 0 0 0 1 0 0 0 0 0, that is, DIP1~DIP5 are OFF ON OFF (according to the default image).

Attention: The base address must not conflict with PC built-in devices (such as COM/LPT ports) or other expansion cards. Common free addresses include 0x300, 0x310, etc. You can use MSD under DOS or Windows Device Manager to view occupied resources.

2.2 Analog input channel configuration (JP3, DG/HG only)

JP3 control input mode:

Single ended mode (default): All 16 channels are based on AGND as a reference, suitable for floating signal sources;

Differential mode: 8 differential channels (CHO~CH7), with positive and negative terminals connected to AI0~AI7 and AI8~AI15 respectively, suitable for grounding reference sources to suppress common mode noise.

The PG version is fixed at 16 single ended and does not have this jumper.

2.3 DMA channel selection (JP7/JP8)

A/D supports high-speed transmission in DMA mode, with the option to select DMA channel 1 or channel 3:

If the PC uses a floppy disk drive (occupying DMA2), it is recommended to choose DMA3;

If using a hard drive (usually not occupying DMA), it is optional, but DMA1 is recommended by default.

Refer to Figure 2.4 in the manual for jumper settings - simply place the short-circuit block in the corresponding "CH1" or "CH3" position.

2.4 Trigger Source Selection (JP4)

A/D conversion can be triggered by internal or external signals:

Internal trigger (default): further divided into software trigger and timer trigger (selected by mode control register);

External trigger: Input rising edge trigger through the 17 pin (ExtTrig) of CN3, suitable for synchronous sampling with external events.

2.5 Interrupt IRQ Setting (JP5)

Supports 9 levels including IRQ3, 5, 6, 7, 9, 10, 11, 12, and 15, with IRQ15 as the default. Insert the jumper cap into the corresponding numbered pin to select the interrupt. If using interrupt transfer mode, it is necessary to ensure that the IRQ is not occupied by other devices (such as IRQ3, which is usually used for COM2, and IRQ7, which is used for LPT1 and should be avoided).