Integration and Optimization of ADLINK DAQ-20xx Synchronous Acquisition Card

ADLINK DAQ/DAQE/PXI-20xx series synchronous data acquisition card on-site deployment and optimization full guide

In the fields of automotive testing, transient signal measurement, biomedicine, and automated testing equipment (ATE), high-precision, multi-channel synchronous data acquisition is the cornerstone for obtaining reliable experimental data. The ADLINK DAQ/DAQE/PXI-20xx series data acquisition card (covering DAQ-2010/2005/2006 and corresponding PCIe/PXI versions) has become a powerful tool for engineers to build precision measurement systems with 4-channel synchronous differential input, a maximum sampling rate of 2MS/s, 16 bit resolution, and flexible analog/digital triggering capabilities. However, any negligence in any link from board ID configuration, signal source grounding type matching, trigger mode selection, and multi card SSI synchronization may lead to data distortion or system failure to start. This article combines the core specifications of the DAQ-20xx series user manual to systematically outline the key nodes and optimization strategies for on-site deployment.

Hardware configuration and jumper settings

1.1 The key role of card ID (SW1) in multi card systems

When installing multiple DAQ-20xx series cards in the same industrial computer or PXI chassis, the system needs to distinguish each device based on the card ID. The onboard 4-digit DIP switch SW1 (default all OFF corresponds to ID 0) provides a total of 16 selectable IDs from 0 to 15. Table 2-1 in the manual provides the complete binary encoding correspondence, for example, ID 5 corresponds to "ON-OFF-ON-OFF".

Deployment points:

In a multi card environment, it is essential to assign a unique ID to each card, otherwise the driver cannot address correctly.

To enable board ID recognition, you need to use W2K_D2kUtil.exe in the D2K-DASK toolset and uncheck the "Ignore Board ID" option (see Figure 2-4). If this function is not enabled, even if different IDs are set for SW1, the system will still ignore it.

1.2 Default Pull Down Mechanism for DIO Initial State (JP4)

The JP4 jumper cap defaults to pulling down the initial state of 24 universal digital I/O channels (provided through 82C55A) to a low level through a 1k Ω resistor to avoid external relay misoperation caused by outputting a high level at the moment of power on. If the application requires a high-level power output, the jumper cap can be removed to disable the pull-down function (see Figure 2-5). Manual recommendation: For applications that drive external solid-state relays or MOSFETs, it is safer to maintain default pull-down.

Signal connection and grounding strategy

2.1 Overview of pin functions of 68 pin VHDCI connector

The DAQ-20xx series uses a 68 pin VHDCI connector (AMP-787254-1) to centralize analog inputs (CHO+~CH3+), analog outputs (DA0OUT/DA1OUT), 24 channels of DIO (PA0~PA7, PB0~PB7, PC0~PC7), universal timer (GPTC0/1), and trigger signals (EXTATRIG, EXTDTRIG, EXTWFTRIG) into a single interface. Tables 3-1 and 3-2 in the manual provide complete pin definitions.

Special note:

Synchronous Digital Input (SDI) is only applicable to DAQ/DAQE/PXI-2010 models (14 bit resolution), and the corresponding pins for 2005/2006 models are marked as NC (unconnected).

The input impedance of the external analog trigger input (EXTATRIG) is 40k Ω in the 2010 model, while it is 2k Ω in 2005/2006. When connecting the signal source, load effects need to be considered.

AOEXTREF allows users to customize the full-scale range of D/A output (within ± 10V), providing flexibility for generating non-standard amplitude waveforms.

2.2 Grounding Type and Differential/Single ended Connection Selection

The DAQ-20xx series only offers 4 differential analog inputs (without single ended mode), which means each channel requires a pair of signal lines (positive and negative). However, the connection strategy varies depending on the type of signal source:

Grounding reference signal source (such as non isolated instrument output): The signal source ground is shared with the acquisition card and can be directly differentially connected (Figure 3-2). The common mode voltage range is ± 11V, and the CMRR can reach up to 97dB (DC~60Hz), effectively suppressing power frequency interference.

Floating signal source (such as thermocouple, transformer output): A bias return path needs to be provided for each differential channel. The usual practice is to parallel a resistor with approximately 100 times the source impedance between the negative terminal of the signal and AIGND (Figure 3-3). If the source impedance is below 100 Ω, the negative terminal can be directly short circuited to AIGND.

Common error: Hanging the negative terminal of the floating signal source causes the input bias current of the instrument amplifier to be unable to flow back, resulting in measurement drift or saturation.

Analog input sampling rate versus resolution tradeoff

3.1 Key parameters for model selection

Model Resolution Maximum Sampling Rate A/D FIFO Typical Application Scenarios

2010 14 bit 2 MS/s 8K sample high-speed transient signal (such as vibration, acoustics)

2005 16 bit 500 kS/s 512 sample high-precision slowly varying signal (such as temperature, pressure)

2006 16 bit 250 kS/s 512 sample extremely low noise high-resolution measurement

The manual tables 1-1 to 1-3 provide detailed information on the -3dB small signal bandwidth, system noise (LSB rms), and CMRR of each model under different input ranges. Taking the 2010 model as an example in the ± 10V range, the -3dB bandwidth reaches 1170kHz, which is sufficient to cover most audio and mechanical vibration frequency bands; The noise of the 2005 system is only 1.2 LSB rms (± 10V), which is suitable for measuring microvolt level signals.

3.2 Scanning timing and counter settings

Although the DAQ-20xx series adopts synchronous sampling (simultaneous conversion of 4 channels), its internal timing is still based on "scan" as the basic unit - triggering synchronous conversion of all enabled channels once per scan cycle. Two core counters determine the acquisition timing:

SI_comounter (24 bits): Set scan interval=SI_comounter/TIMEBASE (default 40MHz internal clock). The minimum SI_comounter for the 2010 model is 20 (corresponding to 2MS/s), the minimum SI_comounter for the 2005 model is 80 (500kS/s), and the minimum SI_comounter for the 2006 model is 160 (250kS/s).

PSC_counter (24 bits): Specify the number of scans to be collected after triggering (in post triggering mode, it is the total number of samples).

Calculation example: If the 2010 model needs to collect 1000 points at a sampling rate of 1MS/s, then SI_comounter=40 (40/40MHz=1 μ s), PSC_comounter=1000 x 4 channels=4000 (actual programming is calculated based on the number of scans, i.e. 1000 scans).

Selection strategy for four triggering modes

Section 4.1.5 of the manual elaborates on four triggering modes that are applicable to different application scenarios:

4.1 Post Trigger

The most commonly used mode is to start collecting a specified amount of data (PSC_comounter) after the triggering event occurs. Suitable for recording responses to external events, such as acceleration signal triggering during impact testing.

4.2 Pre Trigger

Collect M scan data before the triggering event occurs (M is set by the M-counter). Suitable for applications where the triggering time cannot be predicted but the pre triggering state needs to be understood, such as power fault recording.

Key parameter: If the M-enable bit is set to 1, the trigger signal will be ignored until the first M scans are completed, ensuring that complete M pre trigger data can always be obtained (Figure 4-7); If set to 0, the actual amount of stored data may be less than M when triggering early occurrence (Figure 4-6).

4.3 Middle Trigger

Combining pre triggering and post triggering - collecting M scans before triggering and N scans after triggering (N set by PSC_comounter). Suitable for analysis that requires complete context before and after the event, such as motor starting current waveform.

4.4 Delay Trigger

After triggering, the collection will resume after a set delay (DLYcounter). The delay source can be selected from TIMEBASE (maximum 1.638ms) or A/D sampling clock (which can significantly extend the delay range). Suitable for applications that require avoiding triggering momentary interference.

Bus Master DMA and Data Transfer Optimization

For high-speed continuous data collection, software polling can result in extremely high CPU usage. The DAQ-20xx series supports Bus Mastering DMA and is equipped with Scatter/Gather linked list function (Figure 4-13), which solves the pain point of allocating large contiguous memory in operating systems such as Windows.

Implementation mechanism:

Multiple discontinuous memory blocks are concatenated through a DMA descriptor chain table, with each descriptor containing a PCI address, transfer size, and next descriptor pointer.

The maximum transmission capacity for non chain mode is 2M double words (8MB); There is no transmission length limit in chain mode, and it supports circular linked lists to achieve multi buffer continuous collection.

The hardware directly moves the data from the A/D FIFO to the user specified system memory without the need for CPU intervention, freeing up CPU resources for data processing and display.

Deployment suggestion:

Pre allocate larger DMA buffers (such as 64MB per channel) through the ACE tool of ADLINK MAPS Core to reduce interrupt frequency.

For long-term continuous recording, use Ping Pong mode in conjunction with linked list loops to avoid data loss.

Fine tuning of analog triggering and digital triggering

6.1 Five simulation triggering conditions

Manual figures 4-32 to 4-36 show five triggering conditions, all based on two comparison levels, Low_Threshold and High_Threshold (8-bit resolution):

Below Low: Triggered when the signal falls below a low threshold.

Above High: Triggered when the signal exceeds a high threshold.

Inside Region: Triggered when the signal is between high and low thresholds.

High Hysteresis: Triggered when the signal exceeds a high threshold, the low threshold determines the hysteresis hysteresis width (anti noise interference).

Low Hysteresis: Triggered when the signal falls below a low threshold, while a high threshold determines hysteresis hysteresis.

For external analog trigger inputs (EXTATRIG, SRC1), the level range is ± 10V and the resolution is 78mV (Table 4-7). When selecting the ADC input channel as the trigger source (SRC2), the trigger resolution is equal to the full-scale range divided by 256. For example, the resolution at ± 10V range is 78.125mV.

6.2 External digital triggering

EXTDTRIG (A/D dedicated) and EXTWFTRIG (D/A dedicated) accept TTL level signals, with a minimum pulse width of 20ns and programmable selection of rising or falling edge triggering.

SSI Multi Card Synchronization: Breaking the Channel Limit

When more than 4 synchronization channels are required (such as 8-channel vibration analysis), multiple DAQ-20xx cards can be cascaded through the system synchronization interface (SSI). SSI implements daisy chain connection using 20 pin flat cable (ACL-SSI) in the PCI version; In the PXI version, signal routing is completed through the PXI trigger bus (J2) without the need for additional cables.

Six core timing signals that can be synchronized (Table 3-5):

SSI_TIMEBASE (Time Base Clock)

SSIOADCONV (A/D conversion signal)

SSI_SCAN-START (scan start)

SSI_AD_TRIG (A/D triggered)

SSI-DAWR (D/A update)

SSI_CA_TRIG (D/A triggered)

Example of master-slave configuration (4-card synchronization):

Set card 1 as the master device for ADCONV signals, and cards 2-4 as slave devices.

Card 1 receives external digital triggers and initiates data collection, generating ADCONV signals internally.

Card 1 broadcasts ADCONV signals to cards 2-4 through SSI.

Simultaneously convert four cards to achieve 16 channel synchronous sampling.

Important constraint: Each timing signal can independently select a master device, that is, card 1 can be used as the TIMEBASE master device, and card 2 can be used as the AD_TRIG master device. After power on or reset, the timing signals generated internally by each card are used by default.

D/A waveform generation and iterative output

Two 12 bit D/A outputs (LTC7545) support a maximum update rate of 1MS/s and are equipped with a 2K sample FIFO. The waveform generation involves 5 counters (UI_comounter, UC_comounter, IC_comounter, DA-DLY1_counter, DA-DLY2-Counter), which can generate the following patterns:

Post trigger waveform: output immediately after triggering (Figure 4-15).

Delay trigger waveform: After triggering, it is delayed by DLY1 and then output (Figure 4-16).

Repetitive trigger generation: Output a waveform once per trigger, ignoring new triggers during the output process (Figure 4-17).

Iterative waveform: IC_comounter sets the number of repetitions and supports finite (Figure 4-18) or infinite (Figure 4-19) repetitions.

DLY2 Delay: The interval between two consecutive waveform generations (labeled in Figure 4-19).

Stop mode (when triggered by software stop):

Mode I: Stop immediately.

Mode II: Stop after completing the current single waveform.

Mode III: Stop after completing integer multiples of IC_comounter waveform (Figure 4-20~4-22).

GPTC universal timer/counter with eight working modes

Two 16 bit timers/counters (GPTC0/1) support up to 10MHz external clock input and provide 8 programmable modes (Figure 4-23~4-30):

Typical Applications of Mode Function Description

1 Simple Gate Control Event Counting Pulse Counting

2 Single cycle measurement frequency measurement

Analysis of PWM duty cycle for 3 single pulse width measurements

4 Single Gate Control Pulse Generation Programmable Delay Single Pulse

5 single trigger pulses generate external edge triggered single pulses

Generate a single pulse with 6 triggers to trigger each external edge pulse

7 single trigger continuous pulse generation triggers continuous output pulse train

8 consecutive gate control pulses generate continuous pulses during gate control enable period

All modes are software started, with initial values that can be loaded and current count values that can be read back at any time without affecting counting operations.

Calibration and maintenance

The DAQ-20xx series supports automatic calibration without the need for external signal sources or measuring instruments. The onboard 5.000V reference source (temperature drift ± 2ppm/℃, long-term stability 6ppm/1000Hr) ensures calibration accuracy.

Operation process:

Preheat for at least 15 minutes after power on (stability requirements in the manual).

Disconnect all I/O cables (D/A output may change during calibration).

Perform automatic calibration (via software driven API).

Save the new calibration constant to one of the three user modifiable areas in the EEPROM (while recording the calibration date and ambient temperature).

The default factory calibration constant is saved in a separate area, and users can restore the factory values at any time.