Integration and Optimization of ADLINK DAQ-20xx Synchronous Acquisition Card

ADLINK DAQ/DAQE/PXI-20xx series synchronous data acquisition card on-site deployment and optimization full guide

In the fields of automotive testing, transient signal measurement, biomedicine, and automated testing equipment (ATE), high-precision, multi-channel synchronous data acquisition is the cornerstone for obtaining reliable experimental data. The ADLINK DAQ/DAQE/PXI-20xx series data acquisition card (covering DAQ-2010/2005/2006 and corresponding PCIe/PXI versions) has become a powerful tool for engineers to build precision measurement systems with 4-channel synchronous differential input, a maximum sampling rate of 2MS/s, 16 bit resolution, and flexible analog/digital triggering capabilities. However, any negligence in any link from board ID configuration, signal source grounding type matching, trigger mode selection, and multi card SSI synchronization may lead to data distortion or system failure to start. This article combines the core specifications of the DAQ-20xx series user manual to systematically outline the key nodes and optimization strategies for on-site deployment.

Hardware configuration and jumper settings

1.1 The key role of card ID (SW1) in multi card systems

When installing multiple DAQ-20xx series cards in the same industrial computer or PXI chassis, the system needs to distinguish each device based on the card ID. The onboard 4-digit DIP switch SW1 (default all OFF corresponds to ID 0) provides a total of 16 selectable IDs from 0 to 15. Table 2-1 in the manual provides the complete binary encoding correspondence, for example, ID 5 corresponds to "ON-OFF-ON-OFF".

Deployment points:

In a multi card environment, it is essential to assign a unique ID to each card, otherwise the driver cannot address correctly.

To enable board ID recognition, you need to use W2K_D2kUtil.exe in the D2K-DASK toolset and uncheck the "Ignore Board ID" option (see Figure 2-4). If this function is not enabled, even if different IDs are set for SW1, the system will still ignore it.

1.2 Default Pull Down Mechanism for DIO Initial State (JP4)

The JP4 jumper cap defaults to pulling down the initial state of 24 universal digital I/O channels (provided through 82C55A) to a low level through a 1k Ω resistor to avoid external relay misoperation caused by outputting a high level at the moment of power on. If the application requires a high-level power output, the jumper cap can be removed to disable the pull-down function (see Figure 2-5). Manual recommendation: For applications that drive external solid-state relays or MOSFETs, it is safer to maintain default pull-down.

Signal connection and grounding strategy

2.1 Overview of pin functions of 68 pin VHDCI connector

The DAQ-20xx series uses a 68 pin VHDCI connector (AMP-787254-1) to centralize analog inputs (CHO+~CH3+), analog outputs (DA0OUT/DA1OUT), 24 channels of DIO (PA0~PA7, PB0~PB7, PC0~PC7), universal timer (GPTC0/1), and trigger signals (EXTATRIG, EXTDTRIG, EXTWFTRIG) into a single interface. Tables 3-1 and 3-2 in the manual provide complete pin definitions.

Special note:

Synchronous Digital Input (SDI) is only applicable to DAQ/DAQE/PXI-2010 models (14 bit resolution), and the corresponding pins for 2005/2006 models are marked as NC (unconnected).

The input impedance of the external analog trigger input (EXTATRIG) is 40k Ω in the 2010 model, while it is 2k Ω in 2005/2006. When connecting the signal source, load effects need to be considered.

AOEXTREF allows users to customize the full-scale range of D/A output (within ± 10V), providing flexibility for generating non-standard amplitude waveforms.

2.2 Grounding Type and Differential/Single ended Connection Selection

The DAQ-20xx series only offers 4 differential analog inputs (without single ended mode), which means each channel requires a pair of signal lines (positive and negative). However, the connection strategy varies depending on the type of signal source:

Grounding reference signal source (such as non isolated instrument output): The signal source ground is shared with the acquisition card and can be directly differentially connected (Figure 3-2). The common mode voltage range is ± 11V, and the CMRR can reach up to 97dB (DC~60Hz), effectively suppressing power frequency interference.

Floating signal source (such as thermocouple, transformer output): A bias return path needs to be provided for each differential channel. The usual practice is to parallel a resistor with approximately 100 times the source impedance between the negative terminal of the signal and AIGND (Figure 3-3). If the source impedance is below 100 Ω, the negative terminal can be directly short circuited to AIGND.

Common error: Hanging the negative terminal of the floating signal source causes the input bias current of the instrument amplifier to be unable to flow back, resulting in measurement drift or saturation.

Analog input sampling rate versus resolution tradeoff

3.1 Key parameters for model selection

Model Resolution Maximum Sampling Rate A/D FIFO Typical Application Scenarios

2010 14 bit 2 MS/s 8K sample high-speed transient signal (such as vibration, acoustics)