ADLINK PCI-9114 (A) Data Acquisition Card Selection and Configuration Guide



ADLINK PCI-9114 (A) Data Acquisition Card Selection and Configuration Guide

Introduction: The core position of high-precision data acquisition in testing and measurement

High resolution, multi-channel synchronous data acquisition is the cornerstone of accurate measurement in applications such as industrial process monitoring, medical instruments, vibration analysis, and power monitoring. The ADLINK PCI-9114 (A) series is a 16 bit multifunctional data acquisition card based on a 32-bit PCI bus, providing up to 250kHz sampling rate, 32 single ended/16 differential inputs, programmable gain amplification, 1K word FIFO buffer, and 16 isolated digital I/O. With flexible interrupt and trigger mechanisms, it can handle various scenarios from slow temperature acquisition to high-speed dynamic signal analysis. This article will systematically review the differences between PCI-9114 and PCI-9114A, the selection of gain versions (DG/HG), analog input configuration, triggering and data transmission modes, isolation DIO characteristics, and calibration methods, providing engineers with a complete engineering deployment reference.

Model comparison and selection criteria

The PCI-9114 series includes two speed versions and two gain versions, with the following key differences:

Model highest sampling rate gain option (DG) gain option (HG) pre triggered independent counter

PCI-9114 Rev.B1 100kHz 1/2/4/8 1/10/100/1000 None None

PCI-9114 Rev.C2 100kHz 1/2/4/8 1/10/100/1000 available

PCI-9114A 250kHz 1/2/4/8 1/10/100/1000 available

Key selection points:

Speed priority: PCI-9114A provides a 250kHz single channel sampling rate, suitable for high-speed signals such as vibration analysis and acoustic measurement.

Weak signal detection: The HG version provides a maximum gain of 1000 times and can fully utilize a 16 bit resolution (theoretical resolution of about 0.3 μ V) for ± 10mV signals, making it suitable for low-level sensors such as thermocouples and strain gauges.

Pre trigger function: PCI-9114A and Rev.C2 support Pre Trigger, which can collect specified points before and after external trigger signals, suitable for impact testing or fault recording.

Independent Counter: The new version provides a user configurable 8254 Counter # 0, which can be used for frequency measurement or pulse generation.

Analog input configuration and signal connection

3.1 Single ended and differential input selection (JP1)

PCI-9114 (A) supports 32 single ended (SE) or 16 differential (DI) inputs, selected through JP1 jumper:

Single ended mode: All signals are relative to analog ground (AGND), suitable for floating signal sources or short distance transmission (<3m). The maximum number of channels (32), but the ability to resist common mode interference is weak.

Differential mode: Each channel uses a pair of signal lines (AIxH/AIxL) to measure the difference between the two. It can effectively counteract common mode noise and is suitable for long-distance transmission or scenarios with ground potential differences. Reduce the number of channels by half (16 channels).

Engineering suggestion: If the signal source is grounded or there is significant common mode noise (such as in a frequency converter environment), differential mode should be prioritized; If it is a floating signal (such as a thermocouple), single ended mode can be used with cold end compensation.

3.2 Gain and Input Range

The analog input of PCI-9114 (A) is bipolar and does not support unipolar. Corresponding relationship between gain and range:

DG version: 1 →± 10V, 2 →± 5V, 4 →± 2.5V, 8 →± 1.25V

HG version: 1 →± 10V, 10 →± 1V, 100 →± 100mV, 1000 →± 10mV

When selecting gain, it is necessary to ensure that the signal peak does not exceed the range, otherwise saturation clipping may occur. At the same time, try to make the signal occupy more than 80% of the full range to fully utilize the 16 bit resolution.

3.3 Cold end compensation (JP2)

When directly connected using a thermocouple, the onboard cold junction compensation sensor (C.J. Sensor) can be enabled through JP2 and routed to AD channel # 0 or # 16 (depending on single ended/differential mode). The conversion relationship for the calibrated cold junction voltage is: V (mV)=T (K) × 10 (mV/K). After activation, the temperature values measured by the software already include cold end compensation and do not require external reference.

Trigger source and data collection mode

PCI-9114 (A) provides three types of A/D trigger sources:

4.1 Software Trigger (TSSEL=0)

Writing any value to the software trigger register initiates a single conversion. Suitable for low-speed, non periodic data collection (such as manual recording). The completion of the conversion can be determined by polling the AD_SUSY or FF_SF flag.

4.2 Timer Trigger (TSSEL=1)

Using onboard 8254 counters # 1 and # 2 cascaded to generate precise timing pulses, driving A/D conversion. The maximum triggering frequency is limited by the sampling rate (250kHz for PCI-9114A and 100kHz for PCI-9114). By setting the frequency division coefficient through _9114A_Timer (c1, c2), the actual frequency is 2MHz/(c1 × c2).

Engineering note: When the sampling rate of PCI-9114 is 100kHz, it is recommended that c1 × c2 ≥ 20 (2MHz/100kHz); If the trigger frequency is set too high (>maximum sampling rate), the FIFO will overflow and data will be lost.

4.3 External Trigger (EITS=1)

Input an external TTL signal through the Ext_Trg pin of CN4 to trigger A/D conversion. Suitable for synchronizing with external devices such as motion controllers and encoder Z-phase pulses.

Data transmission mode

PCI-9114 (A) is equipped with a 1K word (1024 samples) FIFO for buffering A/D data. Select different transmission modes according to application requirements:

5.1 Software Polling

The simplest way. After software triggering, the FIFO status register is cyclically read, and data is read when FF-EF=1 (FIFO is not empty). Suitable for low-speed acquisition (<1kHz) or scenarios with low real-time requirements.

5.2 FIFO Half Full Polling

The software periodically checks the FIFO half full flag (FF_SF=0 indicates half full). When the sampling rate is 100kHz, the FIFO half full time is about 5.12ms, and the software only needs to check once every 5ms without interruption, resulting in low CPU usage. Suitable for applications that require high speed and do not want complex interrupt programming.

5.3 EOC Interrupt Transmission (INT1=EOC)

After each A/D conversion is completed, an interrupt is generated and the ISR immediately reads the data. Suitable for applications that require point by point real-time processing (such as closed-loop control), but with high interrupt frequency (every 10 μ s at 100kHz), it may increase CPU burden.

5.4 FIFO Half Full Interrupt Transfer (INT1=Half Full)

When the FIFO reaches half full (512 samples), an interrupt is generated, and the ISR reads 512 data at once. Compared to EOC interrupts, the interrupt frequency is reduced by about 512 times, resulting in higher CPU efficiency. Recommended for high-speed continuous acquisition (such as vibration signal recording).

Interrupt clearing key: PCI interrupts are triggered by voltage levels, and after ISR is completed, the interrupt flag must be cleared by calling _9114CLK R_IRQ1() or _9114CLK R_IRQ2(), otherwise subsequent interrupts cannot respond.

Pre Trigger Function

Pre triggering is a unique feature of PCI-9114A and Rev.C2, suitable for scenarios that require recording before and after events, such as impact testing and fault diagnosis.

Working Principle:

Set PTRG=ON, A/D continuously collects and stores data in FIFO, software needs to continuously read to prevent FIFO overflow.

When the external pre trigger signal (PreTrg, CN4 pin9) arrives, 8254 Counter # 0 starts counting down from the preset value N.

Counter # 0 will decrease by 1 every time it receives an A/D trigger pulse, and the A/D will automatically stop when it reaches 0.

The software can read the current value of Counter # 0 to determine whether the collection has ended.

Data storage strategy:

If you need to record N points after triggering, set Counter # 0=N and save the last N data.

If pre trigger data needs to be recorded and N=1 is set, only one additional point will be sampled after triggering, and the waveform at the pre trigger time can be extracted from the data in the FIFO.

N maximum 65535, pay attention to allocating sufficient memory buffer.

Isolate digital I/O

PCI-9114 (A) provides 16 isolated digital inputs and 16 isolated digital outputs, with an isolation voltage of up to 5000VRMS, suitable for industrial sites and interfaces with high voltage or high current equipment.

7.1 Isolation Input (IDI)

Input voltage: 0~24V, threshold high level: 3~24V, low level: 0~1.5V.

The 16 inputs are divided into 4 groups (ID0~3, ID4~7, ID8~11, ID12~15), and each group shares the COM terminal (EICOM1~4).

The input resistance is 4.7k Ω and can be connected through CN2.

Supports two wiring methods: EICOM connected to common ground (sensor output high level valid), or EICOM connected to common power supply (sensor output low level valid, i.e. current injection). Figures 11 and 12 in the manual respectively illustrate.

7.2 Isolation Output (IDO)

The output type is an open emitter current source with an output range of 0.5~50VDC.

The maximum current for a single channel is 500mA, but when 8 channels are working simultaneously, each channel is limited to 60mA (total current limit).

The output is connected through CN3, with EOGND as the common ground and Vpower as the external power source (to be provided by the user).

Inductive load protection: If driving a relay or solenoid valve, an external Fly wheel diode must be connected to Vpower, otherwise the back electromotive force will damage the output transistor.

Interrupt System Architecture

PCI-9114 (A) adopts a Dual Interrupt System, which only occupies one PCI IRQ, but can generate two independent interrupt sources INT1 and INT2:

INT1: From A/D EOC or FIFO half full flag.

INT2: Output from Timer Pacer.

Two interrupts can be enabled simultaneously, and in ISR, the current trigger source is determined through _9114_Get-IRQ_Status() and processed separately. For example, using a FIFO half full interrupt to transmit A/D data, while using a timer interrupt to perform periodic status checks.

IRQ allocation: Automatically allocated by PCI PnP BIOS, users do not need to manually set it. The current IRQ number can be queried through _9114_Get_iRQ_Channel ().

Calibration and maintenance

To ensure measurement accuracy, PCI-9114 (A) requires regular calibration. Five variable resistors (VR1~VR5) on board correspond to different adjustment items:

Number function

VR1 A/D offset adjustment (later stage)

VR2 A/D full-scale adjustment

VR3 Programmable Gain Amplifier Input Offset Adjustment

VR4 Cold End Sensor Offset Adjustment

VR5 PGA output offset adjustment (PCI-9114A/Rev.C2 only)

Key points of calibration process:

PGA offset calibration: Ground AD channel # 16, set maximum gain (HG to 1000, DG to 8), adjust VR3 to make TP1-TP2 voltage approach 0; Set the minimum gain again and adjust VR5 to approach 0. Repeatedly multiple times.

A/D offset calibration: Channel # 16 is grounded, gain=1, adjust VR1 to make the read value between -1~+1.

Full range calibration: Connect an accurate+10V reference voltage, gain=1, adjust VR2 to make the reading between 32766 and 32767.

Cold end calibration: Measure the ambient temperature and adjust VR4 to make the reading conform to the relationship of V (mV)=T (K) × 10.

Calibration cycle recommendation: Once every 3 months for frequent temperature changes or vibration environments; Once every 6-12 months in the laboratory environment.

Common troubleshooting

The A/D reading is always 0 or at full range: check if the input signal is within range, if the JP1 jumper is set correctly, and if the reference voltage is stable.

FIFO overflow error: Sampling rate too high or software polling not timely. Switch to FIFO half full interrupt mode or reduce the sampling rate.

Interrupt does not trigger: confirm that _9114_INT_Source_Control has enabled the corresponding interrupt source, and call the clear function in ISR; Check if PCI IRQ conflicts with other devices.

Pre trigger no response: Confirm that PTRG bit has been set to 1, Counter # 0 has loaded the initial value, and whether the external PreTrg signal level is correct (falling edge trigger).

Isolation output without driver: Check if Vpower is connected and if EOGND is grounded with the load; Is the inductive load connected to a current diode.