ADLINK PCI-9118 series high-speed DAQ card selection and DMA configuration

ADLINK PCI-9118 series high-speed DAQ card selection and DMA configuration

Introduction: Performance bottlenecks and breakthroughs in high-speed data acquisition

In automated testing, vibration analysis, power monitoring, and high-speed process control, the sampling rate, resolution, and data transmission capability of the data acquisition card directly determine the overall performance of the system. Traditional PCI acquisition cards often suffer from data loss due to interrupt response delay or FIFO overflow, especially in Windows non real time operating systems, where high-speed continuous acquisition faces severe challenges. The ADLINK PCI-9118 series achieves seamless data flow of up to 333kS/s by introducing bus master DMA, programmable channel gain queue, and 1k sample FIFO, while providing 12 bit or 16 bit resolution options to meet different accuracy requirements. This article will systematically analyze the selection points, hardware configuration, DMA transfer mechanism, and analog output applications of PCI-9118DG (12 bit/333kS/s), PCI-9118HG (high gain version), and PCI-9118HR (16 bit/100kS/s), helping engineers make optimal decisions in high-speed acquisition projects.

Model comparison and selection decision

The PCI-9118 series includes three models, with the following core differences:

Model A/D Resolution Maximum Sampling Rate Gain Options Input Range Applicable Scenarios

PCI-9118DG 12 bit 333 kS/s x1, x2, x4, x8 bipolar ± 5V~± 0.625V; unipolar 0~10V~1.25V universal high-speed acquisition, such as vibration, audio, transient signals

PCI-9118HG 12 bit 333 kS/s x1, x10, x100 bipolar ± 5V~± 0.05V; single pole 0~10V~0.1V weak signal detection, such as thermocouples, strain gauges, sensors

PCI-9118HR 16 bit 100 kS/s x1, x2, x4, x8 with DG high-precision slow signal, such as temperature, pressure, DC measurement

Selection key:

If the application requires high dynamic range and large signal amplitude changes (such as accelerometers), the DG version provides 12 bit resolution at 333kS/s, with outstanding cost-effectiveness.

If you need to measure millivolt level signals (such as K-type thermocouples), the HG version provides x100 gain, can resolve 0.05V full-scale, and with 12 bit resolution, the theoretical minimum resolution is about 24 μ V (0.05V/4096), which meets the needs of most industrial sensors.

If high DC accuracy is required (such as load cell output), the HR version sacrifices speed for accuracy at a 16 bit resolution (1/65536), making it suitable for precise measurement of slowly changing signals.

Analog input architecture: channel gain queue and automatic scanning

3.1 Flexible configuration of channels and gains

The PCI-9118 series offers 16 single ended or 8-differential inputs (selected through software). The core highlight is the 256 level channel gain queue, which allows users to pre define up to 256 "(channel, gain)" combinations. During the scanning process, the A/D converter samples sequentially in queue order, and each sampling point can have an independent gain setting without the need to repeatedly switch registers in the software. For example, the queue can be set to channel 0 gain 1, channel 1 gain 10, channel 0 gain 1, channel 2 gain 100... to adapt to signal sources of different amplitudes in the same round of scanning, greatly improving the flexibility and sampling efficiency of multi-sensor systems.

3.2 Input Range and Polarity

The DG/HR version supports bipolar (± 5V, ± 2.5V, ± 1.25V, ± 0.625V) and unipolar (0~10V, 0~5V, 0~2.5V, 0~1.25V) modes; The HG version provides bipolar ± 5V, ± 0.5V, ± 0.05V and unipolar 0-10V, 0-1V, 0-0.1V. The input impedance is as high as 1G Ω, with almost no signal source loaded; Overvoltage protection ± 35V continuous, can protect the card from damage in case of wiring errors.

Engineering tip: Try to choose gain levels that are close to 80% or higher of the signal's full range to utilize full resolution. For example, in the DG version, using x4 gain (± 1.25V range) for ± 1V signal is better than x2 (± 2.5V range).

Trigger mode and sampling control

PCI-9118 supports three types of trigger sources to meet different synchronization requirements:

Software trigger: Start a single conversion by writing a trigger register. Suitable for manual testing or low-frequency polling.

Timer trigger (Pacer): The internal 8254 counter generates precise pulses to drive the A/D to continuously sample at a fixed rate. The maximum frequency is limited by the upper limit of the sampling rate.

External trigger (EXTTRG, TTL compatible): Sampling is initiated through external digital signals (such as rotary encoder Z-pulses, optical gates) to achieve synchronization with external events. Can be used in the "waiting for trigger" mode, especially suitable for event driven data collection in process control.

All triggering modes can be combined with automatic scanning and DMA transfer to achieve high-speed background data collection without human intervention.

Data transfer: FIFO and bus master DMA

5.1 Onboard FIFO Buffer

PCI-9118 is equipped with a 1k sample FIFO for temporarily storing converted data. At a rate of 333 kS/s, FIFO can buffer approximately 3 ms of data, providing a time window for software response.