ADLINK PXI-2020/2022 Synchronous Acquisition Card Configuration and Synchronization Guide

ADLINK PXI-2020/2022 Multi Channel Synchronous Data Acquisition Card Application and Configuration Guide

In applications such as vibration analysis, multiphase power measurement, acoustic testing, and transient capture, the phase relationship between multi-channel signals is often equally important as the amplitude. Traditional DAQ cards that use multiplexer polling sampling introduce time skew between channels, resulting in phase information distortion. The ADLINK PXI-2020/2022 series synchronous sampling data acquisition card is designed for this purpose - the series provides 8-channel (PXI-2020) or 16 channel (PXI-2022) fully differential analog inputs, and all channels are sampled simultaneously by independent ADCs to ensure no phase delay between channels. Each channel has a resolution of 16 bits, a sampling rate of 250 kS/s, and is equipped with programmable gain (x 1/x 4), flexible digital triggering, 4 digital I/O channels, and 2 32-bit general-purpose timers/counters. It is suitable for scenarios such as automotive testing, transient measurement, ATE, and laboratory automation. The onboard 16K sample FIFO, combined with Scatter/Gather bus main control DMA, supports continuous high-speed data stream transmission. The PXI trigger bus and star trigger interface can achieve precise synchronization of multiple modules, while the onboard high-precision reference source (5.000V, temperature drift ± 3ppm/° C), combined with automatic calibration function, ensures long-term stability and measurement accuracy.

Product series positioning and key selection indicators

The PXI-2020/2022 series is positioned as a medium speed high-precision multi-channel synchronous sampling platform. Its core value lies in the fact that all channels share the same sampling clock, and each channel is equipped with an independent ADC and signal conditioning path, fundamentally eliminating the inherent inter channel crosstalk and sampling delay of the multiplexing architecture.

Model Differential Input Channel Number Resolution Maximum Sampling Rate (per channel) Gain Options Typical Applications

PXI-2020 8-channel 16 bit 250 kS/s x 1, x 4 medium channel number vibration/acoustics

PXI-2022 16 channel 16 bit 250 kS/s x 1, x 4 high channel number power/structure monitoring

The two models are completely identical in terms of PCB layout and electrical characteristics, except for the number of channels. PXI-2022 achieves 16 channel input through on-board analog switch multiplexing, but all channels still maintain synchronous sampling characteristics.

Performance core indicators (typical values at 25 ° C ± 5 ° C):

Offset error (gain x 1): ± 0.6 mV

Gain error (gain x 1): ± 0.02%

-3dB small signal bandwidth: 1 MHz at x 1, 700 kHz at x 4

System noise: 0.5 mVrms at x 1, 0.2 mVrms at x 4

CMRR（DC）：80 dB

SINAD: 82 dB, ENOB: 13.3 bits

SFDR：87 dB，THD：-85 dB

These indicators indicate that the series performs well in low noise and high dynamic range, making it suitable for high fidelity acquisition of weak signals (such as sensor outputs).

Key points for hardware installation and signal connection

2.1 Anti static and unboxing inspection

The board is a static sensitive device and must be operated on a grounded anti-static pad, wearing an anti-static wristband. The packaging contains board cards ADLINK All-in-One DVD、 Software installation guide and user manual. If damage is found, do not turn on the power.

2.2 PXI Plug and Play Configuration

The board complies with PXI specification Rev2.2 and supports 3.3V and 5V PCI signals. The system automatically assigns IRQ and I/O addresses without the need for manual jumper settings. If the system starts abnormally or experiences unstable operation, it is often due to interrupt conflicts. You can check the BIOS settings or replace the PXI slot.

2.3 Front panel SMA connector

The front panel of PXI-2020/2022 is equipped with 4 SMA coaxial connectors:

TRG IO: Bidirectional external digital trigger input/output port (3.3V LVTTL, 5V withstand voltage), minimum pulse width of 12.5 ns, polarity and edge software programmable.

CLK IN: External time base input (50 Ω AC coupling), input range 1-2 Vpp (sine or square wave), frequency 1-20 MHz, overvoltage protection 2.5 Vpp.

CLK OUT0/OUT1: Time base output (3.3V TTL, 50 Ω output impedance, driving capability 24mA), two outputs of the same source, used to synchronize other devices.

2.4 68 pin VHDCI connector and analog input connection strategy

All analog inputs, digital I/O, timers/counters, and auxiliary function signals are connected through a 68 pin VHDCI female socket. PXI-2020/2022 only supports differential input mode (no single ended option), with AIHx (positive terminal) and AILx (negative terminal) pins provided for each channel.

Grounding reference signal source (such as non isolated instrument output): The positive terminal is connected to AIHx, the negative terminal is connected to AILx, and the signal source ground can be connected to AGND (optional), using the common mode rejection capability of differential input to eliminate ground loop noise.

Floating signal source (such as thermocouple, transformer output): A bias resistor (approximately 100 times the source impedance) needs to be added between the negative input terminal (AILx) and AGND to provide a DC bias circuit for the instrument amplifier. If the source impedance is below 100 Ω, AILx can be directly short circuited to AGND.

Important reminder: pins 2, 5, 8, 11, 14, 17, 20, 23, 36, 39, 42, 45, 48, 51, 54, and 57 of PXI-2020 are NC (unconnected), while PXI-2022 connects AIH8~15 and AIL8~15 channels on these pins.

Analog Input Operation Theory and Timing Control

3.1 Basic acquisition timing sequence

The acquisition engine of PXI-2020/2022 is based on three core counters (all 32-bit):

ScanIntrv (scan interval counter): determines the sampling rate, the formula is sampling rate=TIMEBASE/ScanIntrv. The internal time base is 80 MHz, therefore achieving 250 kS/s at ScanIntrv=320 and 125 kS/s at ScanIntrv=640. The effective range is 4-2 ^ 32-1, with a minimum value of 4 (corresponding to 20 MS/s, but limited by the maximum sampling rate of the ADC).

DataCnt: Specify the total amount of data collected in a single trigger, with a maximum of 2 ^ 31-1.

TribDelayTicks: Specify the delay time between the triggering event and the start of collection, measured in time base cycles (12.5 ns).

Acquisition process (triggered later as an example): After the triggering conditions are met, the acquisition engine generates a sampling signal based on the ScanIntrv value at each rising edge of the time base. The ADC converts the data and stores it in the onboard FIFO (16K samples x 32 bits). When the specified number of DataCnt is reached, the acquisition ends, and then the data is transferred from the onboard FIFO to the host memory through the main line control DMA.

3.2 Time base source selection and external clock

PXI-2020/2022 supports six time base sources, with priority configured by software:

Onboard 80 MHz internal oscillator (accuracy ± 25 ppm)

Front panel AFI [0.. 7] external input

Front panel SMB CLK IN (50 Ω AC coupling, 1-2 Vpp, 1-20 MHz)

PXI Star Trigger (PXI_STAR)

PXI triggers bus line 0 (PXI_TRIG [0])

PXI Backplane 10 MHz Clock (PXI10M)

The external time base input must be a TTL compatible continuous clock with a frequency range of 1-20 MHz (via AFI input) or 1-20 MHz (via SMB CLK IN). Attention: The external clock needs to be continuously stable, otherwise ADC conversion will encounter abnormalities.

3.3 Data Format

All models use 16 bit direct binary encoding. Under the bipolar ± 10V range, FSR-1 LSB corresponds to the code 0xFFFF (9.999695V), zero level corresponds to 0x8000 (0V), - FSR corresponds to 0x0000 (-10V), and LSB=305.2 μ V. Under the bipolar ± 2.5V range, LSB=76.3 μV。

Trigger system and acquisition mode

4.1 Trigger Source Architecture

PXI-2020/2022 provides five trigger sources (Figure 4-6):

Software trigger: directly triggered through function calls, suitable for single point or low-speed data collection.

External digital trigger: TTL edge signal input via SMB TRG IO or AFI [0.. 7], programmable polarity, minimum pulse width of 12.5 ns.

PXI star trigger: receives precise trigger signals from the timing slots of the PXI system, with slot to slot skew<5 ns, suitable for multi module synchronization.

PXI trigger bus [5]: Receive or send trigger signals through the backplane trigger bus to achieve communication between modules.

AFI auxiliary input: 8-channel multifunctional I/O (AFI0~AFI7), configurable as trigger input, time base input, or GPTC signal.

In addition, the board can output internal trigger signals through the SMB TRG IO, AFI0, or PXI trigger bus [5] for controlling external devices or other boards.

4.2 Detailed explanation of four triggering modes

Post trigger: The most commonly used mode is to start collecting a specified amount of data after triggering an event.

Pre trigger: Continuously collect data before triggering, and only retain the most recent M data after triggering. If the trigger occurs before M data collections are completed, the trigger signal will be ignored until M data collections are completed (M-enable mechanism), ensuring the completeness of the pre trigger data volume.

Middle trigger: Save a specified amount of data before and after triggering (M before+N after), suitable for scenarios where the waveform before and after the event needs to be observed. Also supports the M-enable mechanism.

Delay trigger: After triggering, the collection is delayed for a specified time (controlled by a 32-bit trigDelayTicks counter, unit=time base period, maximum delay ≈ 53.7 seconds @ 80MHz) before starting. It is suitable for avoiding transient interference at the moment of triggering.

4.3 Repeated triggering of collection

The ReTrgCnt counter (32-bit) can be used to configure a repeat trigger mode. In Post or Delay mode, DataCnt data is collected after each trigger, and then automatically enters a waiting state, waiting for the next trigger signal until the specified number of repeat triggers is reached. This feature is suitable for applications that require segmented collection of multiple events, and the triggering interval is extremely short (depending only on hardware response time).

Multi module synchronization - PXI trigger bus and SSI

PXI-2020/2022 utilizes the trigger bus (PXI_TRIG [0.. 7]) of the PXI backplane to implement the system synchronization interface (SSI), supporting multi card cascade synchronization in master-slave mode. Three core SSI signals can be flexibly routed to the PXI trigger bus:

SSI_TIMEBASE (PXI_TRIG [0]): The master card outputs its time base clock, while the slave card receives and replaces the internal time base, ensuring that all cards use the exact same sampling clock.

SSI_AD_TRIG (PXI_TRIG [5]): The main card outputs its A/D trigger signal, and the slave card receives it as an external digital trigger.

SSIOADCONV (PXI_TRIG [5] multiplexing): The main card outputs its ADCONV conversion signal, while the slave card receives and replaces the internal conversion signal.

Typical configuration of multi card synchronization (taking 4 PXI-2022 synchronous 64 channel acquisition as an example):

Set card 1 as the SSI_SADCONV master card (outputting ADCONV to PXI_TRIG [5]), and cards 2/3/4 as slave cards (receiving ADCONV from PXI_TRIG [5]);

All cards are configured with the same ScanIntrv value (sampling rate) and DataCnt value;

Card 1 is configured with external digital triggers (such as input from SMB TRG IO), while cards 2/3/4 are configured with trigger sources of PXI_TRIG [5] (i.e. SSI_AD_TRIG);

Start DMA collection for all cards, all cards wait for triggering;

When card 1 receives an external trigger, it generates an ADCONV signal internally and outputs it to PXI_TRIG [5]. All slave cards synchronously receive this signal and start data acquisition.

PXI Star Trigger (PXI_STAR) provides another synchronization method, with propagation delay matching within 1 ns and delay from timing slot to peripheral slot less than 5 ns, achieving more accurate synchronization between modules.

Universal Timer/Counter (GPTC)

The board provides two 32-bit (this series is 32-bit, different from the 16 bit of the 2000 series) general-purpose timers/counters, supporting 8 working modes. The clock source can be selected as internal 20 MHz or external input (up to 10 MHz), and the gate and direction control are flexible:

Mode 1: Simple Gate Control Event Counting

Mode 2: Single cycle measurement (measuring GPTC_GATE signal cycle)

Mode 3: Single pulse width measurement

Mode 4: Software initiates single pulse generation (programmable delay and pulse width)

Mode 5: Edge triggered single pulse generation

Mode 6: Repeatedly trigger single pulse generation (output pulse triggered by each edge)

Mode 7: Edge triggered continuous pulse generation

Mode 8: Software initiates continuous pulse generation (gate control enabled/disabled)

These modes provide hardware level solutions for applications such as speed measurement, PWM generation, pulse counting, etc., without requiring CPU resources.

Calibration and maintenance

PXI-2020/2022 onboard high-precision reference source (ADR02 5V chip, temperature drift ± 3ppm/° C, long-term stability 50ppm/1000Hr), with calibration constants written into the default area of EEPROM at the factory. Users can perform automatic calibration through software after installing the environment (recommended preheating for 15 minutes), without the need for external instruments or manual adjustment of potentiometers. After calibration is completed, the new constant can be stored in one of three user modifiable areas (with date and temperature labels attached) for quick switching under different environmental conditions.

Comparison of accuracy before and after calibration:

Offset error: ≤ ± 0.6mV (gain x 1) before calibration, further improved after calibration

Gain error: ≤ ± 0.02% (gain x 1) before calibration, maintaining high accuracy after calibration

Attention: Before automatic calibration, all external connection cables (especially analog input signal lines) must be removed, as the analog front-end may switch to the internal reference source during the calibration process and may cause voltage changes.

Software Support and Development Ecology

ADLINK provides the D2K-DASK driver library (supporting Windows 98/NT/2000/XP/Vista/7), including DLLs and sample programs, compatible with development environments such as VB, VC++, Delphi, BCB6, etc. This driver library provides complete API functions, covering all functions such as board initialization, channel configuration, trigger settings, DMA transfer, GPTC operation, and calibration. For LabVIEW users, provide DAQ-LabVIEW PnP VI library; For ActiveX/COM environments, provide D2K-OCX controls. All software resources are included in the accompanying All in One DVD.

Development process suggestion:

Call D2K_DeviceOpen to open the device handle;

Call D2K_AI_Config to configure channels, ranges, and gains;

Call D2K_AI_CntConfig to configure ScanIntrv, DataCnt, trigger mode, and trigger source;

Call D2K_AI_CntRead to start DMA continuous acquisition (internal automatic management of Scatter/Gather linked list);

Retrieve data through callback functions or polling;

Call D2K_AI_CntStop to stop the collection.