MOTOROLA CPCI-6020 CompactPCI Single Board Computer

Motorola CPCI-6020 CompactPCI Single Board Computer

The Motorola CPCI-6020 (formerly known as MCP820) is a high-performance 6U Eurocard specification CompactPCI single board computer (SBC) designed specifically for demanding embedded communication and industrial control applications. Its core is equipped with AltiVec ™ The Freescale MPC7410 Reduced Instruction Set (RISC) processor, with a clock speed of up to 500 MHz, provides powerful power for algorithm intensive computing tasks. This manual aims to provide engineers and technicians with comprehensive guidance from unboxing inspection, hardware configuration, system installation to deep functional understanding, ensuring that the board can operate stably and efficiently in the target system.

Product Overview and Core Features

The CPCI-6020 design follows the CompactPCI (PICMG 2.0 R2.1) standard and can serve as a system slot controller, providing system clock and arbitration for the backplane. Its modular design allows users to flexibly expand by adding various daughter boards.

The core hardware features include:

Processor system: MPC7410 processor based on PowerPC architecture, with an external 2MB burst SRAM L2 cache, supporting bus parity check.

Memory system: No onboard memory, supports up to 2GB of ECC (Error Correction Code) protection SDRAM through two independent RAM500 memory expansion sub board interfaces. Each RAM500 module can have a capacity of 128MB, 256MB, or 512MB.

Storage: Provides two types of Flash memory: 32MB (Bank A, onboard) and 1MB (Bank B, socket type). Bank B pre installs PPC bug debugging and diagnostic firmware. Simultaneously equipped with a CompactFlash Type I/II slot, connected via EIDE interface.

PCI architecture: Adopting dual Harrier system memory controllers/PCI host bridge application specific integrated circuits (ASICs), forming two independent PCI bus layers (PCI Bus A and B). PCI Bus A operates at 33MHz and connects most of the onboard I/O and CompactPCI bridges; PCI Bus B can run at 33MHz or 66MHz depending on the capabilities of the installed PMC module.

Rich I/O interfaces:

Network: Two 10BaseT/100BaseTX Ethernet controllers based on Intel 825511T. Usually, the main channel is connected to the front panel RJ-45, and the secondary channel is led out through the rear I/O connector (J5). Routing can be adjusted through customized options.

Serial communication: Two 16550 compatible asynchronous serial ports (UART), two high-speed serial ports that can be configured as synchronous/asynchronous through Zilog ESCC controller.

USB: Four USB 1.1/2.0 host ports (NEC µ PD720101 controller), two of which are located on the front panel and two are routed to the rear I/O.

Expansion interface: A 32/64 bit PMC (PCI Mezzanine Card) slot that supports front and rear I/O. A dedicated Rear Transition Module (RTM) - CPCI-6020-MCPTM-01, used to convert user I/O signals from CompactPCI J3 and J5 connectors into actual connectors on the rear panel (such as EIDE, keyboard/mouse, serial port, Ethernet, etc.).

Other: In the 5E model variant, PS/2 keyboard/mouse interface, floppy disk controller, and speaker output are also supported.

High availability and hot plugging: Supports CompactPCI hot plugging specification (PICMG 2.1) and has Motorola high availability (HA) architecture extension function, supports hot plugging of system slots, and ensures the continuous operation of critical mission systems.

Debugging support: Provides a 190 pin Mictor debugging connector for accessing the processor bus, as well as standard processor JTAG interfaces and RISCWatch heads.

Detailed explanation of hardware installation and configuration

Successful deployment begins with proper hardware preparation. The installation of CPCI-6020 is a systematic process that requires strict adherence to ESD protection and mechanical safety regulations.

1. Unpacking and Inspection:

After receiving the board, it is necessary to immediately inspect the transportation packaging and the board itself for any physical damage, and verify all components that should be delivered. Before handling the board, it is necessary to ensure that the working environment has electrostatic discharge (ESD) protection measures and wear a grounding wristband.

2. Key jumper settings:

Multiple user configurable jumpers are provided on the board to define startup and behavior modes. These jumpers are mainly located on the side of the board and need to be set correctly before installing any daughter board.

J24- Flash Storage Selection: Select which Flash storage to boot the system from. Short circuit 1-2 pins and select 32MB onboard Flash (Bank A); Short circuit 2-3 pins and select 1MB socket type Flash (Bank B, containing PPCBug, factory default).

J22- Harrier Power On Configuration Head: An 8-pin connector that can set the universal power on status bit (PUST [3:0]) of Harrier ASIC by short circuiting different pins, allowing software to read and identify specific configurations.

J21- PMC 66 MHz disabled: Short circuiting this jumper will force PCI Bus B to run at 33MHz, even if the installed PMC module supports 66MHz. This can prevent the secondary Ethernet controller on PCI Bus B from being disabled due to bus acceleration to 66MHz.

J18-+/-12V Power Enable/Disable: Short circuiting this jumper will disable the output of all+12V and -12V power supplies on the board. If the chassis does not provide these voltages, or if the rear transition module (such as SIM card) does not require them, this jumper should be installed.

J17- Bank A Flash Block Lock Enable: After enabling, one or more blocks of Bank A Flash can be locked to prevent erasure.

J20- Bank A Flash Write Protection Enable: Once enabled, the entire Bank A Flash becomes read-only.

J19- Remote switch connector: can be connected to an external switch to achieve the same function as the ABORT and RESET buttons on the front panel.

3. Installation of daughter board:

RAM500 memory expansion module: CPCI-6020 must have at least one RAM500 module installed in order to function properly. The module is installed through the J7 and J28 connectors on the board and supports stacking up and down. During installation, align the connector and secure it with the provided screws and supports.

PMC module: During installation, it is necessary to first remove the corresponding blocking plate on the front panel, align the PMC module with the J11-J14 connectors on the board and stabilize it, and fix it with screws. In non hot swappable chassis, it must be operated in a power-off state.

CompactFlash card: Insert directly into the J15 connector on the board, paying attention to aligning Pin 1.

4. Installing the motherboard into the chassis:

Slot selection: CPCI-6020 must be installed in the CompactPCI system slot marked with a triangle symbol.

Installation steps: Open the fixed wrench on the board (note: there are multiple types of wrenches, such as Elma and Rittal), and smoothly push the board along the guide rail until the pre alignment pin contacts the backplane connector. Then close the fixing wrench until it locks, and finally tighten the fixing screws at both ends of the front panel.

Hot swappable precautions: For chassis that support hot swappable, peripheral cards can be installed or removed without the system being powered on. But before removing CPCI-6020 itself (system controller), its operating system and applications must be shut down normally through software. CPCI-6020 itself does not support hot swappable LED status and requires manual confirmation that the software has stopped.

5. Installation of the rear transition module:

CPCI-6020-MCPTM-01 needs to be installed in the corresponding slot at the back of the chassis. Important note: This module itself does not support hot swapping. Before installing or removing it, the power supply of the front-end CPCI-6020 card paired with it must be removed or turned off first. The installation process is similar to that of a motherboard, and attention should also be paid to ESD protection and mechanical alignment.

In depth analysis of system architecture and functional modules

The excellence of CPCI-6020 lies in its precise architecture design.

1. Dual Harrier ASIC core:

Two Harrier ASICs are the core hubs of the board, labeled Harrier A and B.

Harrier A: As the main bridge, it connects the processor bus to PCI Bus A. Manage most system resources, including some system memory (via memory expansion connectors), all Flash storage NVRAM/RTC、 On board I2C EEPROM, two UART, and bridging to all devices on PCI Bus A (such as 21154 PCI to PCI bridge, main Ethernet, PCI/ISA bridge). It is also responsible for top-level interrupt control.

Harrier B: Connect the processor bus to PCI Bus B. Mainly manages another part of the system memory and provides bridging and interrupt control for PCI Bus B (PMC slots and secondary Ethernet controllers).

This discrete design enhances I/O bandwidth and system reliability.

2. Memory subsystem:

The memory is fully provided by the RAM500 expansion module, which is connected to Harrier A and B through two independent 72 bit wide (64 bit data+8-bit ECC) buses. The ECC function can correct single bit errors, detect double bit errors, and greatly improve data integrity. The memory size can be flexibly configured by installing RAM500 modules of different capacities.

3. PCI bus structure:

PCI Bus A (33 MHz): Provides a local CompactPCI bus that complies with the CompactPCI 2.0 specification through the Intel 21154 PCI to PCI bridge chip, capable of driving up to 7 peripheral slots. At the same time, the bus is also connected to Winbond W83C554F PCI/ISA bridge (providing EIDE and ISA bus functions), main Ethernet controller, NEC USB host controller, as well as Zilog ESCC and CIO chips for synchronizing serial ports.

PCI Bus B (33/66 MHz): specifically designed to serve PMC expansion slots and secondary Ethernet controllers. Its operating frequency is determined by the automatic detection of the M66EN pin status of the installed PMC module (which can be covered by J21 jumper). If a 66MHz PMC is detected, the bus will run at 66MHz and the secondary Ethernet controller will be disabled (as it only supports 33MHz).

4. High availability support:

CPCI-6020 communicates with the bridge board in Motorola HA chassis through J4 connector to achieve hot plugging and fault switching of system slots. The mechanism includes:

BD_SEL # signal: controls whether the backplane power supply supplies power to the board.

HEALTHY # signal: Report to the backplane whether the power status of the board is normal.

Communication with remote HSC: Through dedicated signals on J3 (HSC-REQ #, HSC-GNT #, HSC-FLOAT, HSC-EJECT #), remote hot swappable controllers are allowed to request and take over control of the local CompactPCI bus, enabling the replacement of system controllers without interrupting service.

5. Debugging and Diagnosis:

PPCBug firmware: stored in Bank B Flash, it is a powerful command-line based debugging monitoring program and hardware diagnostic kit. It is responsible for power on initialization, hardware self-test, providing memory/register viewing and modification, breakpoint debugging, program download (via serial port or network), and starting the operating system.

Physical debugging interface: The 190 pin Mictor connector provides full speed trace access to the processor bus; The standard JTAG interface supports processor core debugging.

Firmware usage and system startup

After the system is powered on or reset, the initialization sequence of PPCBug firmware will be automatically executed, which includes MPU register setting, cache invalidation, hardware device (PCI bridge, memory controller, etc.) initialization, memory capacity detection, clock calibration, PCI device enumeration, etc. After completion, the onboard fault LED will turn off and the MCP820Bug>or PPC Bug>prompt will be displayed on the console (default connection to the front panel COM19600bps, 8N1).

Users can interact with the system through a variety of PPCBug commands:

System configuration command: CNFG is used to view and modify board information blocks (such as serial number, Ethernet address); ENV is used for detailed configuration of startup parameters, such as automatic boot switch, boot device sequence, network parameters, watchdog settings, etc.

Memory and I/O operation commands: MD/MM (display/modify memory), RD/RM (display/modify registers), PF (set port format).

Program debugging commands: GO (execute program), BR (set breakpoint), GT (run to temporary breakpoint), DS (disassemble).

Diagnostic command: Use the SD command to switch to the diagnostic directory and run integrity tests for specific hardware such as memory, UART, PCI bus, real-time clock, etc.

Boot commands: RB (boot from Flash), PBOOT (boot from disk), NAB (boot from network).

Special note: Extreme caution should be exercised when reprogramming Flash using commands such as PFLASH. Incorrect operations may erase Bank B Flash containing PPC bugs themselves, causing the board to fail to boot.

Application areas and compliance

CPCI-6020, with its powerful processing capabilities, rich I/O, high reliability, and modular design, is widely used in telecommunications infrastructure (such as base station controllers, media gateways), industrial automation, military embedded computing, and any field that requires robust, high-performance CompactPCI solutions.

This product is designed to comply with multiple international standards, including:

Safety standard: UL/EN/IEC/CSA 60950-1.

Electromagnetic compatibility: comply with FCC Part 15 Class A, EN 55022 Class A, CISPR 22, etc. (usually tested in compliance systems).

Environment and Reliability: Meets partial requirements of NEBS GR-63-CORE (Environment), GR-1089-CORE (EMC and Safety), as well as ETSI EN 300 019 series standards.

Environmental Directive: Compliant with the European Union's Directive on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment (RoHS).