ADLINK ACL-7122 Digital I/O Card Installation and Programming

ADLINK ACL-7122 144 bit Digital I/O Card Installation and Programming Practical Guide

In industrial automation production lines, old ISA bus equipment is still widely used in CNC machine tools, semiconductor test benches, and power monitoring systems. The ACL-7122 144 bit parallel digital I/O card launched by ADLINK has become the preferred choice for many system integrators due to its six sets of high-density analog 8255 PPI channels and OPTO-22 compatible interface. As the original factory gradually stops production, how to correctly deploy, configure, and program this card has become a practical challenge for maintenance engineers. This article is based on the official technical manual, providing a complete set of operating instructions from hardware installation, address jumpers, interrupt settings to C language programming examples to help you extend device life in existing systems.

Product positioning and core features

ACL-7122 is a half size (183mm × 111mm) ISA expansion card that provides 144 TTL/DTL compatible digital I/O lines, divided into 6 channels, each channel simulating an Intel 8255 programmable peripheral interface (PPI), including PA, PB 8-bit ports and PC ports (divided into high 4 bits and low 4 bits). Its main features include:

High driving capability: The PA/PB port outputs a minimum high level of 2.4V and a current of 24mA; the PC port also has a current of 24mA and can directly drive relays or optocouplers.

Flexible Interrupt: Each channel's PC0 (rising edge trigger) and PC3 (falling edge trigger) can generate hardware interrupts, supporting IRQ 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, and supporting multi card sharing of the same interrupt (tri state output).

Output read back: Even if the port is set to output, the current output latch status can still be read for easy fault diagnosis.

Fully compatible with Advantech PCL-722, it can directly replace old models.

Data transmission rate: typical 300KB/s, up to 500KB/s, meeting the requirements of high-speed digital control.

Open box inspection and anti-static treatment

The kit includes ACL-7122 card and user manual (3rd edition, 1997). After receiving the goods, please check the PCB for any physical damage, especially paying attention to whether the 50 pin IDC connector pins are bent. Due to the sensitivity of CMOS devices on the card to static electricity, it is essential to:

On the grounding anti-static pad;

Wear an anti-static wrist strap and share the ground with the mat;

After removing from the anti-static bag, hold only the edge of the card to avoid touching the gold fingers and IC.

It is recommended to press all plug-in ICs (such as 8255 compatible chips) to ensure that they are not loose during transportation.

Jumper and DIP switch configuration

There is a SW1 (5-bit DIP switch) on the card for base address setting, JP0~JP5 for channel interrupt enable, JP6 for global IRQ selection, and JP7 for selecting 144 bit or 96 bit modes.

1. I/O mode selection (JP7)

144 bit mode (default): occupies 32 consecutive I/O ports and provides all 6 channels (CH0~CH5).

96 bit mode: occupying only 16 ports, disabling CH4 and CH5, suitable for systems with tight address space.

Maintain 144 bit mode unless conflicting with other card addresses.

2. Base address setting (SW1)

The base address must be within the range of 200h~3F8h and cannot conflict with the system reserved address (such as COM/LPT). The manual provides a detailed truth table. Taking the example of setting the base address to 2C0h:

Map address lines A9~A4 to DIP1~DIP6, where A9 is fixed at 1 (OFF) and hardware forces A3~A0 to 0.

The binary value of 2C0h is 10-11 million, which means A9=1, A8=0, A7=1, A6=1, A5=0, A4=0, A3~A0=0.

DIP switch status: A9（DIP1）=OFF(1)，A8（DIP2）=ON(0)，A7（DIP3）=OFF(1)，A6（DIP4）=OFF(1)，A5（DIP5）=ON(0)，A4（DIP6） In 144 bit mode, it has no effect (Don't care) and can remain ON.

Table 2.2 of the manual lists switch combinations for commonly used addresses such as 200h, 2C0h, 3A0h, etc. The default factory setting is 2C0h.

Note: A4 is invalid in 144 bit mode because port 32 requires A4 to be 0, but the switch position can be ignored; The 96 bit mode requires precise definition of A4 according to Table 2.3.

3. Interrupt settings (JP6 and JP0~JP5)

JP6: Select global IRQ, a total of 11 options available, default IRQ15 (usually idle). If there is a conflict with other devices, it can be changed to IRQ9, 10, etc. Insert the jumper cap into the corresponding pin pair.

JP0~JP5: Enable interrupts corresponding to CHO~CH5. Each jumper has three states:

D (Disabled): This channel does not generate interrupts.

E (Enable): Enable interrupt, the triggering edge is determined by the combination of PC0 and PC3 (see below).

P (Programmable): Programmable interrupt, requires PC4 to be pulled down simultaneously to activate the interrupt, allowing software to mask the interrupt.

Trigger edge logic:

In E-mode: PC0 is triggered by the rising edge (Low → High), and PC3 is triggered by the falling edge (High → Low). If PC0 is High and there is no jump, it will not be triggered.

In P mode: except for the above edge conditions, PC4 must be Low to allow interrupt output; If PC4=High, all interrupts are prohibited.

This design allows for software shutdown interrupts or cascading multiple interrupt sources through PC4.

Definition of connector pins and external wiring

The six 50 pin IDC male heads (CHO~CH5) on the card are arranged with OPTO-22 standard pins and can be directly connected to ADLINK's TB-24R (24 relay outputs), TB-24P (24 optocoupler inputs), or TB-16P8R (16 inputs+8 outputs) terminal boards. The PA, PB, and PC of each channel each occupy 8 bits, among which the high 4 bits (PC4~PC7) and low 4 bits (PC0~PC3) of the PC can be independently set for input/output.

Typical connection method:

Control external relays: Set PA/PB as the output, connect TB-24R through a ribbon cable, and drive one relay coil for each output position.

Read limit switch: Set PC or PA as input, connect TB-24P, and isolate external 24V signal with optocoupler.

Attention: All I/O are TTL level (high ≥ 2.0V, low ≤ 0.8V). If high voltage/high current loads need to be driven, they must be isolated through OPTO-22 module or relay board to avoid damaging the card.

Register Structure and Programming Fundamentals

The I/O mapping of ACL-7122 is based on four registers (PA, PB, PC, control word) per channel, with the base address set to B. Therefore:

CH0: B+0 (PA), B+1 (PB), B+2 (PC), B+3 (CW)

CH1: B+4~B+7

CH2: B+8~B+11

CH3: B+12~B+15

CH4: B+16~B+19

CH5: B+20~B+23

Control word format (written to CW register):

D7=1 (mode setting flag), D6~D5=00 (mode 0), D4=port A direction (0=output, 1=input), D3=PC high 4 bit direction (0=output, 1=input), D2=port B direction, D1=PC low 4 bit direction, D0 unused (usually 0).

For example, set all ports of CH0 as output: control word=1000 0000b=0x80.

Set the PA input, PB output, PC input, and PC output for CH1: D4=1, D3=1, D2=0, D1=0 → Binary 1 001 1 000 0=0x98.

Power on default: All ports automatically enter input mode, and the output latch is a random value. If output is required, the control word must be written to define the direction first, and then the data must be written to the corresponding port.

Output Read Back: Even if set as output, executing inportb (B+PA) can still read the current latch value, making it easier to verify program logic.

Detailed Analysis of Interrupt Programming

Using interrupts requires three steps:

Hardware settings: Select IRQ through JP6 and set JPx to E or P mode.

Software initialization: Write the appropriate I/O direction to the control word of the corresponding channel (note that PC0/PC3 must be inputs to receive external triggers, as they are interrupt source pins).

Clear interrupt status and allow interrupt: The manual provides a "false read" technique: first write an index to the control word register of the channel (i.e. base address+3,+7,...), and then read once from the PC port of this channel to clear the suspended interrupt and re enable it. Example code:

outportb(BASE+3, 0x00); //Point to CH0 CW (in fact, just write any CW address)

dummy = inportb(BASE+2); //Read PC0, clear interrupt

This operation will reset the interrupt trigger logic, enabling subsequent edge detection.

Writing ISR: Under DOS or Windows 3.1/95, interrupts can be mounted using the setvect() function of d_dos_getvect/d_dos_detvect or Borland C. In the service program, it is necessary to read the corresponding PC port to determine the interrupt source (PC0 or PC3 level), but please note that the input is not latched, and the order cannot be determined. Only the current state can be recognized.

Self triggering test: The manual provides an example program that generates interrupts through software simulation - by applying a jump to the PC0 or PC3 pin of a certain channel (by writing to the PC port), the interrupt can be triggered for debugging.

Interrupt sharing: Due to the output being in three states, multiple ACL-7122s can share the same IRQ. ISR needs to poll the status of each card to determine which card has generated an interrupt.

Common troubleshooting

Based on the manual and on-site experience, the following is compiled:

Possible causes and solutions for the fault phenomenon

The system is unable to recognize card base address conflicts or check for SW1 settings beyond the range. Refer to Appendix A to confirm unoccupied addresses (such as 2F8h as COM2, 3F8h as COM1, etc.)

If there is no level change in the output port, forget to write the control word or if the control word is incorrect, make sure to write CW first and then write the data; Check D7=1, correct direction position

Interrupt does not trigger JPx not set to E/P, or IRQ is blocked to confirm JPx jumper; Check if the IRQ in the system BIOS is assigned to ISA instead of PCI; Viewing the masking register with inportb (0x21) in DOS

Interrupt triggered multiple times or randomly triggered but not cleared correctly (false read not executed). In each ISR, a read operation must be performed on the PC port to clear the edge detection flag

When multi card sharing is interrupted, the response is abnormal. ISR does not poll all cards. In ISR, read the PC ports of each card in sequence to determine which one has changed

Insufficient high-level output driver, unused buffer or heavy load PA/PB. The minimum high-level is 2.4V and the current is 24mA. If the load is too large, a driving transistor needs to be added

Upgrade replacement suggestion

Considering that ACL-7122 has been discontinued, if the original card is damaged and cannot be repaired, we can consider:

Search for second-hand channels (such as Artisan Technology Group) to purchase refurbished parts, and ensure that the functions are functioning properly.

Replacing with PCI or PCIe bus digital I/O cards (such as ADLINK PCI-7230 or PCIe-7432) requires rewriting the drivers and applications, resulting in higher porting costs.

Using ISA to PCI bridge card, but there are compatibility risks.

For production lines that are still using ISA industrial computers, it is recommended to keep 1-2 ACL-7122 and keep complete records of jumper settings to cope with sudden failures.