ADLINK ACL-8112 Data Acquisition Card Configuration and Programming

2.6 D/A reference voltage setting

The output range of D/A is determined by the reference voltage (internal -5V or -10V, or external input):

Internal reference selection (JP2): further select -5V or -10V from JP1 (DG/HG) or JP8 (PG);

External reference: Connect from pin 31 (ExtRef1) and pin 12 (ExtRef2) of CN3 respectively, with a maximum voltage range of ± 10V (unipolar output 0~Vref).

Output calculation formula: Vout=- VRef × (DAn/4096). For example, when Vref=-10V, the digital quantity is 0 → 0V, 4095 →+9.9976V.

2.7 Timer Clock Source (JP6, DG/HG only)

The clock source for counter 0 can choose between an internal 2MHz or an external clock (via the 37 pin ExtCLK of CN3). Default internal 2MHz, suitable for frequency generator mode; An external clock can be used for event counting.

2.8 A/D input maximum range (JP9, PG version only)

The PG version sets the maximum input range to ± 5V or ± 10V through JP9, and combines it with the gain value (× 1~× 16) to determine the actual range (such as ± 0.625V for gain × 16 at ± 10V).

Definition of Signal Connections and Terminals

ACL-8112 provides three connectors:

CN1 (20 core IDC): Digital output channels DO0~DO15;

CN2 (20 core IDC): Digital input channels DI0~DI15;

CN3 (37 core D-Sub): Analog input/output, timer/counter, and external reference signal.

3.1 Key points of analog input wiring

Floating ground signal source (single ended mode): The positive end of the signal is connected to AIn, and the negative end is connected to AGND (see Figure 3.4). Multiple floating ground sources need to be shared.

Ground source (differential mode): The positive terminal of the signal is connected to AIn+, and the negative terminal is connected to AIn -, using a differential suppression ground loop (see Figure 3.5).

Differential source (differential mode): If the signal source itself is a differential output (not grounded), a short circuit should be added between the AGND and the negative terminal of the signal to avoid damage to the device due to high common mode voltage (see Figure 3.6).

Important: AGND is an analog ground and is connected to the digital ground (GND) at a single point inside the board. It cannot be short circuited externally to avoid introducing digital noise.

3.2 Analog Output

AO1 (30 pins) and AO2 (32 pins) output 0~Vref (unipolar) with a load capacity of ± 5mA. If a voltage based industrial standard (such as 0~10V) is required, an internal reference of -10V can be set.

3.3 Digital I/O

All DIOs are TTL compatible, with input high level ≥ 2.0V, low level ≤ 0.8V; output high level ≥ 2.4V (source current 0.4mA), low level ≤ 0.4V (sink current 8mA). It can directly drive 74LS series logic circuits or optocouplers.

3.4 Timer/Counter

CN3 provides CLK (pin 37), GATE (pin 36), and COUP0 (pin 35) for counter 0. CLK can be selected as an internal 2MHz or external input, GATE level controls counting enable, and COUP outputs pulse or level status.

Register programming model

The register mapping of ACL-8112 is the core of low-level programming. After setting the base address to BASE, the offset of each functional register is as follows:

Offset read operation and write operation

BASE+0 counter 0 current value counter 0 initial value

BASE+4 A/D low byte D/A channel 1 low byte

BASE+5 A/D high byte (including DRDY bit) D/A channel 1 high byte

BASE+6 DI low byte D/A channel 2 low byte

BASE+7 DI high byte D/A channel 2 high byte

BASE+8 Unused Interrupt Request

BASE+9 does not use A/D range control

BASE+10 Unused Channel Multi Channel Switch

BASE+11 unused mode control

BASE+12 not triggered by software A/D

BASE+13 Unused DO Low Byte

BASE+14 unused DO high byte

4.1 A/D Conversion Process

Write BASE+10 to select the channel (CL3~CL0 are channel numbers, when DG/HG is differential, set CS0/CS1 to 1 at the same time);

Write BASE+9 to set gain and polarity (see Tables 4.2-1 to 4.2-4);

Write BASE+11 selection mode (0=software trigger+polling, 2=timer+DMA, 6=timer+interrupt, etc.);

Trigger conversion:

Software mode: Write any value to BASE+12;

Timer mode: Set the initial value of counter 1/2 (BASE+1/BASE+2);

External mode: waiting for the rising edge of ExtTrig;

Read data: When polling the DRDY bit (bit4) of BASE+5 to 0, read BASE+4 (low 8 bits) first, then read BASE+5 (high 4 bits+DRDY), and the DRDY will be automatically cleared.

4.2 Timer Operation (8254)

Write control word into BASE+3 (format: SC1/SC0 select counter, RL1/RL0 select read/write mode, M2/M1/M0 select mode, BCD select binary/BCD);

Counter 0 is available for users to freely use (programmable as square wave generator, monostable, event counting, etc.);

Counter 1 and 2 are cascaded to form an A/D sampling clock with a frequency of 2MHz/(c1 × c2), where c1 and c2 are 16 bit initial values (1~65535). The maximum theoretical frequency is 500kHz, but due to the limitation of ADC conversion time, it is actually ≤ 100kHz.

C Language Library Function Programming Guide

ADLINK provides the Borland C/C++library (header file 8112. h) for DOS environment, with a total of 23 functions covering initialization DIO、DA、AD、 Timer operation and advanced DMA/interrupt transmission.

5.1 Initialization and Multi Card Switching