ADLINK PCI-9114 (A) Data Acquisition Card Selection and Configuration Guide

4.3 External Trigger (EITS=1)

Input an external TTL signal through the Ext_Trg pin of CN4 to trigger A/D conversion. Suitable for synchronizing with external devices such as motion controllers and encoder Z-phase pulses.

Data transmission mode

PCI-9114 (A) is equipped with a 1K word (1024 samples) FIFO for buffering A/D data. Select different transmission modes according to application requirements:

5.1 Software Polling

The simplest way. After software triggering, the FIFO status register is cyclically read, and data is read when FF-EF=1 (FIFO is not empty). Suitable for low-speed acquisition (<1kHz) or scenarios with low real-time requirements.

5.2 FIFO Half Full Polling

The software periodically checks the FIFO half full flag (FF_SF=0 indicates half full). When the sampling rate is 100kHz, the FIFO half full time is about 5.12ms, and the software only needs to check once every 5ms without interruption, resulting in low CPU usage. Suitable for applications that require high speed and do not want complex interrupt programming.

5.3 EOC Interrupt Transmission (INT1=EOC)

After each A/D conversion is completed, an interrupt is generated and the ISR immediately reads the data. Suitable for applications that require point by point real-time processing (such as closed-loop control), but with high interrupt frequency (every 10 μ s at 100kHz), it may increase CPU burden.

5.4 FIFO Half Full Interrupt Transfer (INT1=Half Full)

When the FIFO reaches half full (512 samples), an interrupt is generated, and the ISR reads 512 data at once. Compared to EOC interrupts, the interrupt frequency is reduced by about 512 times, resulting in higher CPU efficiency. Recommended for high-speed continuous acquisition (such as vibration signal recording).

Interrupt clearing key: PCI interrupts are triggered by voltage levels, and after ISR is completed, the interrupt flag must be cleared by calling _9114CLK R_IRQ1() or _9114CLK R_IRQ2(), otherwise subsequent interrupts cannot respond.

Pre Trigger Function

Pre triggering is a unique feature of PCI-9114A and Rev.C2, suitable for scenarios that require recording before and after events, such as impact testing and fault diagnosis.

Working Principle:

Set PTRG=ON, A/D continuously collects and stores data in FIFO, software needs to continuously read to prevent FIFO overflow.

When the external pre trigger signal (PreTrg, CN4 pin9) arrives, 8254 Counter # 0 starts counting down from the preset value N.

Counter # 0 will decrease by 1 every time it receives an A/D trigger pulse, and the A/D will automatically stop when it reaches 0.

The software can read the current value of Counter # 0 to determine whether the collection has ended.

Data storage strategy:

If you need to record N points after triggering, set Counter # 0=N and save the last N data.

If pre trigger data needs to be recorded and N=1 is set, only one additional point will be sampled after triggering, and the waveform at the pre trigger time can be extracted from the data in the FIFO.

N maximum 65535, pay attention to allocating sufficient memory buffer.

Isolate digital I/O

PCI-9114 (A) provides 16 isolated digital inputs and 16 isolated digital outputs, with an isolation voltage of up to 5000VRMS, suitable for industrial sites and interfaces with high voltage or high current equipment.

7.1 Isolation Input (IDI)

Input voltage: 0~24V, threshold high level: 3~24V, low level: 0~1.5V.

The 16 inputs are divided into 4 groups (ID0~3, ID4~7, ID8~11, ID12~15), and each group shares the COM terminal (EICOM1~4).

The input resistance is 4.7k Ω and can be connected through CN2.

Supports two wiring methods: EICOM connected to common ground (sensor output high level valid), or EICOM connected to common power supply (sensor output low level valid, i.e. current injection). Figures 11 and 12 in the manual respectively illustrate.

7.2 Isolation Output (IDO)

The output type is an open emitter current source with an output range of 0.5~50VDC.

The maximum current for a single channel is 500mA, but when 8 channels are working simultaneously, each channel is limited to 60mA (total current limit).

The output is connected through CN3, with EOGND as the common ground and Vpower as the external power source (to be provided by the user).

Inductive load protection: If driving a relay or solenoid valve, an external Fly wheel diode must be connected to Vpower, otherwise the back electromotive force will damage the output transistor.

Interrupt System Architecture

PCI-9114 (A) adopts a Dual Interrupt System, which only occupies one PCI IRQ, but can generate two independent interrupt sources INT1 and INT2:

INT1: From A/D EOC or FIFO half full flag.

INT2: Output from Timer Pacer.

Two interrupts can be enabled simultaneously, and in ISR, the current trigger source is determined through _9114_Get-IRQ_Status() and processed separately. For example, using a FIFO half full interrupt to transmit A/D data, while using a timer interrupt to perform periodic status checks.

IRQ allocation: Automatically allocated by PCI PnP BIOS, users do not need to manually set it. The current IRQ number can be queried through _9114_Get_iRQ_Channel ().