ADLINK PCI-9812/10 high-speed synchronous acquisition card

Deep technical analysis and engineering application of ADLINK PCI-9812/10 20MHz synchronous sampling data acquisition card

Introduction: The core position of high-speed synchronous sampling in complex signal processing

In applications such as radar, sonar, medical imaging (ultrasound, gamma cameras), non-destructive testing, and communication baseband signal analysis, the amplitude, phase, and spectral information of signals are crucial. These applications typically require multiple channels to simultaneously collect signals at extremely high sampling rates for subsequent complex operations such as FFT, digital filtering, and correlation detection. Traditional multiplexing acquisition cards cannot meet the requirements of phase sensitive measurements due to time skew between channels.

The Linghua PCI-9812/10 was born to overcome this challenge. Its biggest feature is that each of the four channels is equipped with an independent A/D converter, which can achieve true synchronous sampling, and the sampling rate can reach up to 20 MS/s (single channel) or 5 MS/s per channel (four channels simultaneously). This card adopts a 32-bit PCI bus, supports bus master DMA, and directly transfers data to the host memory, greatly reducing the burden on the CPU. Its flexible triggering mechanism and multiple clock sources (internal/external sine/external square wave) enable precise synchronization with external systems, making it suitable for various complex testing environments.

Hardware architecture and core specifications

2.1 Analog input channel

Number of channels: 4 single ended inputs (BNC interface, J1~J4）。

Resolution: PCI-9812 is 12 bits, PCI-9810 is 10 bits (with no missing codes).

Input range: ± 1V or ± 5V (factory default ± 1V, 50 Ω input impedance) can be selected through the solder pads on the board.

Input impedance: It can be configured as 50 Ω (low impedance, suitable for high-frequency signals), 1.25k Ω, or 15M Ω (high impedance) by combining pads (COLO and CO5V). Default 50 Ω is used for matching 50 Ω coaxial cables. Attention: If configured with high impedance (15M Ω) and large input bias current (about 15mA), a low impedance signal source must be connected to provide a return path, otherwise it will damage the A/D converter.

2.2 Clock System

Internal clock: The onboard 40MHz crystal oscillator generates a sampling clock through a 16 bit even frequency divider (2~1024).

External clock: supports two types of external clock sources——

Sine wave clock (J5 BNC, 50 Ω AC coupling, 2Vpp input).

Square wave clock (JP1 pin 1, TTL level, 50 Ω DC coupling).

Regardless of the type of clock, it passes through a frequency divider, so the external clock frequency is at least twice the required sampling rate (with a minimum division factor of 2).

2.3 Trigger System

Trigger source: software trigger (calling DMA start function), external analog trigger (any analog input channel can set trigger level through DAC) and external digital trigger (JP1 pin 3, TTL edge).

Trigger mode:

Software trigger: Directly initiate data collection.

Post trigger: Start collecting a specified number of samples after the triggering event occurs.

Pre trigger: Collection starts before triggering and stops when a triggering event occurs.

Middle trigger: Collection is performed before and after triggering, and the number of samples after triggering is set by the post trigger counter.

Delay trigger: After triggering an event, a specified number of sampling clocks are delayed before collection.

2.4 FIFO and Data Flow

The total capacity of the onboard FIFO is 32K words (16 bit width). When 4 channels are sampled simultaneously, the FIFO depth of each channel is 8K samples; When using only 2 channels (0 and 1), each channel has 16K samples; When only one channel is used, all 32K samples belong to that channel.

The data is transferred to the host memory through the bus master DMA without the need for CPU intervention. The PCI controller (AMCC S5933) is responsible for handling bus arbitration and burst transmission.

Register programming and underlying control

PCI-9812/10 occupies 9 32-bit I/O addresses (Base+0 to Base+0x20), and all accesses must be 32-bit wide. The key registers include:

Offset write function and read function

Base+0 ADC channel enable (CHO~CH3) -

Base+4 clock division factor (2~1024, even) -

Base+8 trigger mode selection -

Base+C trigger level (8-bit DAC) -

Base+10 trigger source and polarity -

Trigger counter value after Base+14-

Base+18 FIFO control (clear FIFO, clear trigger flag) FIFO status (half full, empty, overflow, trigger detection, etc.)

Base+1C acquisition enable -

Base+20 clock source selection and frequency labeling -

Channel enablement rule: Hardware only allows three valid channel combinations - CH0 only, CH0+CH1, and all four channels. Not supporting combinations such as CHO+CH2 or only CH2+CH3, as the internal hardware scanning sequence is fixed (0 → 1 → 2 → 3 cycles).

Divider: The written value must be even, with a minimum of 2. The internal clock source is 40MHz, so the maximum sampling rate is 20MHz; The frequency of the external clock source is not limited (but it must meet the requirement of ≤ 20MHz after frequency division).

Trigger detection: When simulating a trigger, the onboard DAC generates a comparison voltage, which is compared with the input signal, and the comparator output edge is used as the trigger event. The triggering delay is about 350ns, which has a slight impact on high-speed acquisition and needs to be considered in the timing design.

Working mode and data throughput limitations

4.1 Synchronous Sampling and Multi Card Synchronization

Due to the independent ADC of each channel, the theoretical synchronization deviation of the four channels in the same card is extremely small (clock edges arrive simultaneously). But when multiple cards need to be synchronized, even if the same external clock source is used, there may be a phase shift of half a sampling clock cycle due to the internal frequency divider (÷ 2) of each card. The manual clearly states that full synchronization of multiple cards cannot be achieved unless the user designs an external clock allocation and carefully calibrates the delay.

4.2 Continuous acquisition length limit

This is the most critical engineering constraint in high-speed data acquisition. Total data throughput=sampling rate x number of channels x 2 bytes. For example, at 4 channels and 20MS/s, the total throughput is 160MB/s, far exceeding the theoretical peak of 132MB/s and the actual effective bandwidth (usually<100MB/s) of the PCI bus (32-bit/33MHz). Therefore:

If the total throughput rate is ≤ PCI effective bandwidth, DMA can be used for continuous transfer, with a maximum data volume of 64MB (limited by the PCI controller), which is specifically limited by the available continuous memory of the host.

If the total throughput rate is greater than the PCI bandwidth, the data can only rely on FIFO cache, and the maximum number of continuously collected samples is limited by the FIFO capacity -16K samples per channel for 2 channels and 8K samples per channel for 4 channels. If exceeded, FIFO overflow occurs (status bit FIFOOR set).

Section 5.5 of the manual provides detailed decision-making steps and emphasizes that at high speeds, CPU processing power and hard disk write speed can also become bottlenecks. It is recommended to use double buffering technology to achieve infinite continuous acquisition (but software cooperation is required, and processing speed must keep up).

C/C++software libraries and drivers

5.1 Overview of Library Functions

Linghua provides Borland C++library for DOS and DLL (function name prefix with W_) for Windows 95/98. The core functions include:

_9812Initialize: Initialize the card, return the base address, IRQ, and PCI master status.

_9812_Set_Clk_Src/_9812_Set_Clk-Rate: Set the clock source and division factor.

_9812_Set_Trig: Configure trigger mode, source, polarity, level, and post trigger count value.

_9812_AD_DMA_Start: Start DMA acquisition, specify channel combination (1/2/4), total number of samples, and buffer address (DOS) or memory handle (Windows).

_9812_AD_DMA_Status: Query the collection progress and status (in progress, waiting for trigger, delayed, completed).

_9812_AD_DMA_Stop: Terminate collection prematurely and return the number of transferred samples.

Windows specific functions: W_9812_ Alloc_DMA_Sem (allocate contiguous physical memory), W_9812_Sree_SMA_Sem, and W_9812_Get_Sample (for accessing data in languages such as VB).

5.2 Data Format

Each 16 bit data sample contains 12 (or 10) bits of ADC data (MSB aligned), 3 bits of universal digital input (DI0~DI2), and 1 bit of trigger detection flag. The Least Significant Bit (LSB) has 4 zeros in 12 bit mode and 6 zeros in 10 bit mode, and the software needs to perform truncation or shift processing.

5.3 Programming Process

Typical collection process:

_9812Initialize obtains resources.

_9812_Set_Clk_Src and _9812_Set_Clk-Rate set the clock.

_9812_Set_Trig configuration triggered.

Allocate memory for (Windows) W_9812_ Alloc_DMA_Sem.

_9812_AD_DMA_Start starts collection (starts immediately in software triggered mode; waits for triggering in other modes).

Loop call _9812_daD_DMA_Status to monitor the status until completion.

Process data and call _9812_AD_DMA_Stop (if necessary).

Release resources (_9812_Close and W_9812_Sree_SMA_Sem).

Calibration and debugging tools

6.1 Hardware Calibration

Onboard 8 adjustable potentiometers (VR1~VR8), corresponding to bias and full-scale calibration of four channels respectively. Factory calibrated, it is recommended to recalibrate every 3 months when there are significant environmental changes. Calibration requires a high-precision voltage source (± 1V or ± 5V), guided by calibration software (9812til. exe) to gradually adjust the corresponding VR, so that the read value is within the error range.

6.2 Practical Tools (9812til. exe)

9812til under DOS provides three main functions:

System configuration: Display card number, base address, IRQ, and PCI master status.

Calibration: A graphical interface that indicates which VR should be adjusted for each step and displays the ADC sampling values in real-time.

Functional testing: Trigger mode, polarity, trigger level, channel number, and post trigger count value can be set to display the collected waveform in a graphical manner, helping users intuitively verify trigger behavior and sampling effect.

This tool is highly valuable for troubleshooting and performance evaluation, and it is recommended to use it to verify hardware status before writing applications.

Typical application scenarios and key points of system integration

7.1 Applicable Applications

Radar intermediate frequency digitization: synchronous sampling of I/Q signals, requiring high sampling rate and low phase error.

Ultrasound imaging: Multi channel array probes synchronously receive and generate high-quality images.

Video digitization: Synchronize sampling of RGB or YUV components of composite video signals.

Vibration/shock testing: Multiple accelerometers synchronously collect data for modal analysis.

7.2 System Integration Precautions

Input impedance matching: For high-frequency signals (such as>10MHz), a 50 Ω impedance should be selected and the cable characteristic impedance should be matched to avoid reflection.

High impedance mode warning: If selecting a 15M Ω input, be sure to connect a low impedance source to prevent charge accumulation from burning out the ADC.

Clock quality: The external clock requires low jitter, and the sine wave needs to have sufficient amplitude (2Vpp). The square wave needs to meet the TTL level (2.4V~5V) and have a fast rising edge.

Bus bandwidth planning: At 4 channels of 20MS/s, the sustained data rate is 160MB/s, which exceeds the PCI bandwidth. At this point, we can only rely on FIFO to collect a limited length (8K samples per channel), or reduce the sampling rate/number of channels. If long-term continuous collection is required, a double buffering scheme must be adopted and the processing speed must be matched.

Multi card synchronization: If multi card synchronization is necessary, it is recommended that all cards share the same external clock source and measure the phase difference of each card's sampling clock through an oscilloscope, and then compensate for it through software delay (or accept a fixed phase difference).

Maintenance and troubleshooting

Startup failure: Check if the PCI slot supports bus master (mostly supported), and if the BIOS has assigned IRQ and I/O addresses.

Data overflow (FIFOOR set): Indicates that the data transfer rate is lower than the sampling rate, which can reduce the sampling rate, decrease the number of channels, optimize PCI bus load, or use a higher performance motherboard.

Trigger failure: Check if the trigger level is set within the signal range, if the polarity is correct, and if the external trigger signal meets electrical specifications.

Driver installation: Windows 95/98 requires inserting a card and booting up first. The system prompts to specify the CD path X: Win95inf9812 when installing the driver. If using Windows NT or higher versions, a separate PCIS-DASK driver package needs to be purchased.

Selection and Upgrade Suggestions

PCI-9812/10 is still in service in many high-end testing systems today. If the system originally used a low-speed ISA or PXI acquisition card, upgrading to this card can significantly improve sampling rate and synchronization. Attention should be paid when selecting:

If only 10 bit resolution is required, choosing PCI-9810 would be more cost-effective.

If higher precision (>12 bits) or higher sampling rate (>20MS/s) is required, Linghua's new generation PCIe or PXIe products, such as PCI-9846 (16 bit, 40MS/s), should be considered.

Software migration: Existing programs based on DOS or Win95 can continue to be used, but for modern Windows systems, it is recommended to use PCIS-DASK (NT/2000/XP) or Linux drivers (to be developed independently or consulted with Linghua).