ADLINK USB-2405 Dynamic Signal Acquisition Module Deployment Guide

Coupling method: DC coupling preserves the DC component in the signal, suitable for pressure sensors or slowly changing signals; AC coupling filters out DC bias through a high pass RC network (-3dB @ 0.4Hz), suitable for AC dynamic signals (such as vibration acceleration).

IEPE incentive: After enabling, each channel outputs a constant current of 2mA to the BNC center conductor and automatically switches to AC coupling. The voltage signal returned by the sensor is superimposed on the excitation voltage and sent to the ADC through a DC blocking capacitor. Note that IEPE mode is only used for piezoelectric sensors with built-in amplifiers and cannot be used for ordinary voltage sources.

4.2 Data Format and Range

The input range is fixed at ± 10V, 24 bit data is represented by binary complement, and the least significant bit (LSB) is 1.19 μ V. The numeric code 0x000000 corresponds to 0V, 0x7FFFFF corresponds to+9.99999881V, and 0x800000 corresponds to -10V. After reading the original code, the software needs to convert it into a voltage value.

4.3 Sampling rate and anti aliasing

The sampling clock is generated by DDS and can be adjusted in 0.0003Hz steps within 1kHz~128kHz. Two working modes are automatically switched by sampling rate:

High resolution mode (≤ 52.734kHz): The digital filter extraction ratio is 512, providing better in band noise performance;

High speed mode (>52.734kHz): Extract ratio of 256, expands bandwidth but slightly increases noise floor.

The internal digital filter is a multi-stage FIR with an out of band attenuation of 100dB, combined with an RC low-pass (about 500kHz cutoff) at the input to jointly suppress aliasing. The frequency response curve shows that the flatness is better than ± 0.15dB within 0.49 times the sampling rate, and it quickly rolls off after exceeding this frequency.

Trigger mechanism and collection mode

USB-2405 provides rich trigger sources and modes to adapt to different transient or continuous acquisition requirements.

5.1 Trigger Source

Software trigger: Immediately start collecting after calling the API, with no external signals.

External simulation trigger: Choose one of the four input channels as the trigger source and set the high/low level threshold (24 bit resolution). The triggering condition can be "Below Low" or "Above High".

External digital trigger: TTL level input through GPIO pin, programmable to have effective rising or falling edge, with a minimum pulse width of 20ns.

5.2 Trigger Mode (Key)

Post Trigger: Collect a specified amount of data after triggering (without pre triggering).

Pre Trigger: Continuously store data from the start of collection until the triggering event arrives, retaining the first N samples before triggering, and may continue collection thereafter (depending on the mode). If the number of collected samples is less than N when the trigger arrives, ignore the trigger until the condition is met.

Delay Trigger: After triggering, wait for the specified delay count (32 bits, maximum 2 Ω² -1) before starting data collection.

Middle Trigger: Simultaneously collect M samples before and N samples after triggering (M+N ≤ 8k), suitable for recording the complete waveform before and after the event.

Gated Trigger: Data is only collected during periods when the trigger signal is at a high (or low) level, and pauses when the level is reversed.

Re Trigger: In post trigger or delayed trigger mode, multiple triggers can be set, with a fixed number of points collected after each trigger and repeated until the specified number of times.

Important limitation: In pre trigger and mid trigger modes, the buffer size is fixed at 8k sampling points (total of all channels), so M+N must be ≤ 8192. Special attention should be paid when designing the collection length.

Programmable functional I/O applications

GPIO can be configured through software to the following modes (only one can be selected at a time):

Static digital I/O: Read and write high and low levels through APIs, used to control external indicator lights or read switch status.

Frequency/Event Counter: measures the frequency of the input signal (up to 4MHz), an internal 32-bit counter that can count the number of pulses within a specified time.

PWM output: By setting the initial count value and pulse width count value, a square wave with variable frequency and duty cycle is generated, with a maximum frequency of 4MHz.

Digital trigger input: As an external digital trigger source for continuous analog acquisition (see previous section).

Synchronous sampling clock input: The continuous clock signal (1k-128kHz) input from the external can drive ADC sampling, achieving multi module synchronization. Note that multiple USB-2405 must share the same external clock and trigger to ensure phase consistency between channels.

Calibration and precision maintenance

7.1 Calibration Architecture

The module integrates a precise reference voltage source and TrimDAC (digital to analog adjustment) internally, and is calibrated and stored with constants in the factory area of EEPROM (read-only) at the factory. The user area can store subsequent self calibration results.