ADLINK PXIS-3320 PXI chassis installation troubleshooting

ADLINK PXIS-3320 15 Slot 6U PXI Chassis Deployment and Troubleshooting Guide

In the fields of high-end testing and measurement, semiconductor automation, military electronics, and scientific research experiments, the PXI platform has become the preferred architecture for system integration due to its modularity, high bandwidth, and precise synchronization capabilities. ADLINK PXIS-3320 is a 19 inch 6U PXI/CompactPCI chassis, providing 1 system slot and 14 peripheral slots, supporting high power density configurations, equipped with hot swappable redundant power supplies and powerful cooling systems. This article will provide engineers with a complete engineering deployment manual from the aspects of backplane architecture, power budget, system monitoring, hardware installation, common troubleshooting, and preventive maintenance.

Product positioning and selection comparison

The PXIS-3320 series is divided into two models:

PXIS-3320: Standard Edition, equipped with 2 hot swappable cPS-H325/AC power modules, with a total output power of 500W (250W per module), suitable for most conventional PXI testing systems.

PXIS-3320/1000W: High power version, equipped with 4 identical power modules, with a total output power of 1000W, designed for power intensive peripherals such as high-speed digitizers (high sampling rate ADCs), arbitrary waveform generators, high-power digital I/O drivers, RF communication modules, etc.

Both models comply with PXI Rev. 2.2 and CompactPCI (PICMG 2.0) specifications, support 6U cards (also compatible with 3U modules through adapter boards), have physical dimensions of 484mm x 295mm x 398mm (length x width x height, excluding handles), weigh approximately 23kg, and can be installed in a rack or placed on a desktop.

Selection suggestion: If the total power consumption of modules in the system (+5V,+3.3V,+12V, -12V) is less than 450W, the standard version is sufficient; If the estimated power exceeds 500W or N+1 redundancy is required (4 power supplies support 3+1 backup), the 1000W version must be selected. Recommend pairing with ADLINK cPCI-6840 or cPCI-6860A high-performance system controllers, or implementing remote host expansion through PCI-8570/PXI-8570 remote control modules.

Backplane architecture and synchronization characteristics

The PXIS-3320 backplane model CBX-6015 adopts a height of 6U and is physically arranged with 15 slots (the system slot is located at the leftmost end, i.e. Slot 1).

2.1 System Slot (Slot 1)

Occupying 2 slot widths, it can install 1 or 2 slot 6U PXI/cPCI controllers. This slot provides standard PCI bus signals (32/64 bits, 33/66MHz) and implements PCI communication through the P1 connector, while the P2 connector provides PXI specific signals (trigger, clock, local bus, etc.).

2.2 Star trigger slot (Slot 2)

Slot 2 is a star shaped trigger main slot, which sends trigger signals to Slot 3~Slot 15 through dedicated point-to-point connections (PXI_STAR0~PXI_STAR12) on the backplane. The channel skew is less than 1ns, making it suitable for multi module systems that require precise synchronization (such as multi-channel synchronous sampling). To use star trigger, a dedicated star trigger controller module must be installed in this slot.

2.3 Peripheral Slot (Slot 3~Slot 15)

There are a total of 14 peripheral slots that can accommodate standard 6U PXI or CompactPCI modules. Each peripheral slot is equipped with:

PXI trigger bus (8-wire): shared among all slots, used for transmitting trigger signals or clocks between modules to achieve timing coordination.

PXI local bus (14 lines): connects adjacent slots (left and right) to form a daisy chain, used for high-speed auxiliary communication or analog signal transmission, without occupying PCI bandwidth. Note that the local bus is disconnected between Slot 1 and Slot 2, in accordance with PXI specifications.

10MHz reference clock (PXI_CLK10): allocated from the system slot to all peripheral slots, independently buffered, with inter slot skew<1ns, supporting external clock input (injected through the P2 pin of Slot 2).

2.4 Multi segment PCI bus structure

In order to support 15 slots, the backplane divides the PCI bus into three independent segments (via bridge chips):

Bus # 1: Slot 1 (system)+Slot 2~Slot 6 (a total of 6 slots)

Bus # 2: Slot 7~Slot 12 (6 slots)

Bus # 3: Slot 13~Slot 15 (3 slots)

Each segment has independent IDSEL, REQ/GNT, and clock allocation, effectively reducing bus load and ensuring signal integrity. Interrupt Routing (INTA~INTD) is allocated according to rotation priority, as detailed in the manual table "Bus Segments and Interrupt Routing".

Detailed explanation of power system and power budget

3.1 Power module specifications

Each cPS-H325/AC power module is a PICMG 2.11 compatible 3U CompactPCI module, supporting 100~240VAC wide voltage input (47~63Hz), with the following single module output capabilities:

Typical maximum current of voltage rail

+5V 25.0A 33.0A

+3.3V 18.0A 33.0A

+12V 5.0A 5.5A

-12V 0.5A 1.0A

Note: The maximum power of each voltage rail is limited by the total module power of 250W, and the combined output of+5V and+3.3V cannot exceed the overall limit of the module.