TEKTRONIX VX4240 VXIbus protocol waveform digitizer/analyzer module

TEKTRONIX VX4240 VXIbus protocol waveform digitizer/analyzer module

Product identity and applicable scenarios

Tektronix VX4240 is a modular waveform digitizer/analyzer based on the VXIbus protocol, designed specifically for C or D-sized VXIbus mainframes. Its core positioning is a high-precision, multifunctional signal measurement and analysis tool. It integrates a 12 bit A/D converter and RISC processor, which can be widely used in laboratory signal testing, industrial equipment monitoring, electronic system development, and other scenarios. It can complete the entire process of capturing, storing, and analyzing DC to high-frequency AC signals.

Detailed explanation of core technical parameters

1. Hardware core configuration

Specific specifications of hardware components

A/D converter with 12 bit resolution, 10 MHz sampling rate, supports high-precision conversion from analog signals to digital signals

The INMOS T800 floating-point transputer processor is responsible for signal analysis and module control

Memory configuration standard 256K word sampling memory; Optional 512K word (Option 01) or 1M word (Option 02) expansion memory

Storage module with 128K bytes of RAM (running memory) and 128K bytes of EPROM (program storage); Non volatile memory (storing calibration parameters)

Two BNC input interfaces (SIG IN+, SIG IN -) and one DB25S connector (S3) for input/output; Support TTL level triggered input/output, clock input/output, ARM input/output

2. Key parameters for signal capture

(1) Frequency and Sampling Performance

Frequency range: DC to 5 MHz, with a attenuation index of -3 dB ± 1 dB at the 5 MHz frequency point, a roll off of -6 dB/octave in the 5-10 MHz frequency band, and a roll off of -18 dB/octave in the 10-20 MHz frequency band.

Sampling frequency: Programmable range from 0.005 Hz to 10 MHz, supports three clock sources - internal clock, external clock (TTL level, 50 Ω load, DC to 10 MHz), VXIbus 10 MHz ECL clock.

Sampling interval: 100 ns to 200 s (100 ns step) in internal/external clock mode, with a minimum period of 100 ns for external clock.

Clock accuracy: The internal clock has an annual drift of 5 ppm, ensuring long-term sampling stability.

(2) Input feature configuration

Voltage range:

Calibration range: ± 0.5 V, ± 1 V, ± 2 V, ± 5 V, ± 10 V, ± 20 V, ± 50 V, ± 100 V (8 levels in total, higher accuracy).

Virtual range: Supports any non calibrated voltage range within 100V, and achieves 12 bit weight allocation through Tek's self-developed virtual range circuit, with better performance than some 14 bit digitizers.

Input type: differential input (CMRR common mode rejection ratio:>40 dB from DC to 1 kHz, typical value for 50 Ω load>50 dB, typical value for 1 M Ω load>60 dB), single ended input.

Coupling methods: AC coupling, DC coupling, and grounding are available, suitable for different signal types (such as AC coupling isolating DC components).

Input impedance:

50 Ω (± 1%, parasitic capacitance<20 pF): suitable for high-frequency signal measurement.

1 M Ω (± 3%, parasitic capacitance<20 pF): suitable for measuring low-frequency and high impedance signals.

929 k Ω (± 2%, parasitic capacitance<20 pF): Suitable only for voltage ranges of 50 V and 100 V.

Resolution (12 bits): The smaller the voltage range, the higher the resolution, such as 0.48828 mV/bit for ± 1 V range and 48.828 mV/bit for ± 100 V range.

(3) Trigger and delay control

Trigger source: Supports 5 types of trigger sources, which can be flexibly combined (AND/OR logic of any two trigger sources):

External TTL edge trigger (programmable positive/negative edge).

Dual voltage threshold triggering (± 0 to ± 100% full-scale, 8-bit resolution).

VXIbus TTL trigger (8-channel programmable trigger line selection).

The VXIbus command is triggered.

Software triggering (receiving T command to start).

Trigger mode:

Pre trigger (CP): Store data before triggering and store a specified number of samples after triggering.

Post trigger (CT): default mode, data is stored after triggering, and the default sample size is memory size -100.

Central Trigger (CC): The trigger event is located in the center of the memory, with half of the samples stored before and after.

Free Run (CF): Uncontrolled by trigger control, continuously sampling after receiving the T command until receiving the stop command.

Record mode (CR): Automatic re triggering, storing data according to the set number of samples/records, supporting up to 65534 records.

Trigger delay: Programmable range of 200 ns to 420 s (200 ns step), delay uncertainty ≤ 200 ns+1 sampling clock cycle, meeting the requirements of precise timing control.

Trigger heavy arming time: In recording mode, it is one sampling clock cycle and supports fast continuous sampling.

3. Signal analysis function (40+core functions)

(1) Time domain analysis function

Function Name Description

Calculate the difference between the steady-state high level (100% point) and steady-state low level (0% point) of the signal using peak to peak voltage (AK), and return the maximum/minimum/average values

Rise time (AR) measures the time it takes for a signal to rise from 10% steady state to 90% steady state, and returns the maximum/minimum/average values