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  • GE IS200TRPGH1B - TERM. BD., TRIP PRIMARY GAS
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  • GE IS200TRPGH1B - TERM. BD., TRIP PRIMARY GAS

    110V-380V
    1A-30A
    5W-130W
    1 year
    30
    United States, France, Japan, Viet Nam, Australia, Russia, Germany, Italy, Arabia
    IS200TRPGH1B - TERM. BD., TRIP PRIMARY GAS
    • ¥12000.00
      ¥24520.00
      ¥12000.00
      ¥12000.00
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    Weight:3.600KG
    • Quantity:
    • (Inventory: 33)
Description
IS200TRPGH1B - TERM. BD., TRIP PRIMARY GAS

GE IS200TRPGH1B - TERM. BD., TRIP PRIMARY GAS

Part Number IS200TRPGH1B Manufacturer General Electric Country of Manufacture As Per GE Manufacturing Policy Series Mark VI Function Module Availability In StockIS200TRPGH1B is a Primary Trip Terminal Board manufactured and designed by General Electric as part of the Mark VI Series used in gas turbine control systems. The I/O controller regulates the TRPG terminal board. Three voting circuits in TRPG feature nine magnetic relays that connect to three trip solenoids, or Electrical Trip Devices (ETD). The primary and emergency sides of the interface to the ETDs are formed by the TRPG and TREG working together. For gas turbine applications, TRPG also accepts inputs from eight Geiger-Mueller flame detectors. 

There are two board types as follows: The H1A and H1B versions include three voting relays built into each trip solenoid for TMR applications. For simplex applications, the H2A and H2B versions have one relay per trip solenoid. MARK VI SYSTEMS: The VTUR board interfaces with the TRPG terminal board in Mark VI systems. TRPG is connected to the VME rack, which houses the VTUR board, through cables with molded plugs. Systems using simplex and TMR are both supported. MARK VIe SYSTEMS: The PTUR packs on TTURH1C control TRPG in Mark VIe systems. 

The D-type connectors on TTURH1C, which is connected to TRPG, accept the I/O packs as input. Systems using simplex and TMR are both supported. INSTALLATION: The flame detectors (if utilized) are attached directly to the second terminal block, while the three trip solenoids are wired to the first I/O terminal block. The flame detectors are linked with the power to J3, J4, and J5. J1 receives 125 V dc power for the trip solenoids, and J2 supplies power to the TREG board. OPERATION: The main protection solenoids are tripped by the main protection relays on TRPG, which are controlled by the I/O board. In TMR applications, a relay ladder logic two-out-of-three voting circuit is used to vote the three inputs in hardware. The I/O board keeps track of supply voltages for diagnostic purposes and tracks the current flow in its relay driver control line to determine whether to electrify or de-electrify the relay coil contact status. 

The diagnostics check each normally closed contact from a relay on the TRPG board to make sure it is functioning properly. The controller transmits the primary Overspeed trip, which is subsequently transmitted to the I/O pack or board and finally to the TRPG terminal board. Together with the TREG board, which is managed by the VPRO emergency Overspeed system, TRPG functions. The TRPG/TREG combination may drive three ETDs. 

 DIAGNOSTICS: The TRPG diagnostics are run by the I/O board. These include feedback from the trip solenoid relay driver and contact, the solenoid power bus, and the excitation voltage for the flame detector being too low or excessive. If any of the signals becomes abnormal, a diagnostic warning is generated (beyond limits). The terminal board's connectors JR1, JS1, and JT1 each have their own ID device that the I/O board queries. If a discrepancy is found, a hardware incompatibility fault is generated. The terminal board serial number, board type, revision number, and plug location are all encoded on the read-only ID device chip.Module manufactured by General Electric as part of the Mark VI/VIe Series used in gas turbine sppedtronic control systems

OTHER INFORMATION

• Up to 1.26 GHz Pentium® III processor with 256 KB advanced  transfer cache  

• Up to 512 MB PC-133 SDRAM using a single SODIMM  

• Internal AGP SVGA controller with 4 MB display cache  

• 133 MHz system bus via Intel® 815E chipset  

• Dual Ethernet controllers supporting 10BaseT and 100BaseTX  interfaces  

• Optional PCI dual channel Ultra160 SCSI  

• Up to three (two with rear I/O support) PMC expansion sites  (IEEE-P1386 common mezzanine card standard, 5 V)  

• Up to 1 GB bootable flash on secondary IDE (optional)  

• Two 16-bit and two 32-bit programmable timers  

• 32 KB of nonvolatile SRAM  

• Software-selectable watchdog timer with reset  

• Remote Ethernet booting  

• Optional IDE hard disk drive  

• VME64 modes supported:  A32/A24/D32/D16/D08(EO)/MBLT64/BLT32  

• VMEbus interrupt handler, interrupter and system controller  

• Includes real time endian conversion hardware for littleendian and big-endian data interfacing (patent no. 6,032,212)  

• Enhanced bus error handling  

• Passive heat sink


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