Integration and Optimization of ADLINK DAQ-20xx Synchronous Acquisition Card

2005 16 bit 500 kS/s 512 sample high-precision slowly varying signal (such as temperature, pressure)

2006 16 bit 250 kS/s 512 sample extremely low noise high-resolution measurement

The manual tables 1-1 to 1-3 provide detailed information on the -3dB small signal bandwidth, system noise (LSB rms), and CMRR of each model under different input ranges. Taking the 2010 model as an example in the ± 10V range, the -3dB bandwidth reaches 1170kHz, which is sufficient to cover most audio and mechanical vibration frequency bands; The noise of the 2005 system is only 1.2 LSB rms (± 10V), which is suitable for measuring microvolt level signals.

3.2 Scanning timing and counter settings

Although the DAQ-20xx series adopts synchronous sampling (simultaneous conversion of 4 channels), its internal timing is still based on "scan" as the basic unit - triggering synchronous conversion of all enabled channels once per scan cycle. Two core counters determine the acquisition timing:

SI_comounter (24 bits): Set scan interval=SI_comounter/TIMEBASE (default 40MHz internal clock). The minimum SI_comounter for the 2010 model is 20 (corresponding to 2MS/s), the minimum SI_comounter for the 2005 model is 80 (500kS/s), and the minimum SI_comounter for the 2006 model is 160 (250kS/s).

PSC_counter (24 bits): Specify the number of scans to be collected after triggering (in post triggering mode, it is the total number of samples).

Calculation example: If the 2010 model needs to collect 1000 points at a sampling rate of 1MS/s, then SI_comounter=40 (40/40MHz=1 μ s), PSC_comounter=1000 x 4 channels=4000 (actual programming is calculated based on the number of scans, i.e. 1000 scans).

Selection strategy for four triggering modes

Section 4.1.5 of the manual elaborates on four triggering modes that are applicable to different application scenarios:

4.1 Post Trigger

The most commonly used mode is to start collecting a specified amount of data (PSC_comounter) after the triggering event occurs. Suitable for recording responses to external events, such as acceleration signal triggering during impact testing.

4.2 Pre Trigger

Collect M scan data before the triggering event occurs (M is set by the M-counter). Suitable for applications where the triggering time cannot be predicted but the pre triggering state needs to be understood, such as power fault recording.

Key parameter: If the M-enable bit is set to 1, the trigger signal will be ignored until the first M scans are completed, ensuring that complete M pre trigger data can always be obtained (Figure 4-7); If set to 0, the actual amount of stored data may be less than M when triggering early occurrence (Figure 4-6).

4.3 Middle Trigger

Combining pre triggering and post triggering - collecting M scans before triggering and N scans after triggering (N set by PSC_comounter). Suitable for analysis that requires complete context before and after the event, such as motor starting current waveform.

4.4 Delay Trigger

After triggering, the collection will resume after a set delay (DLYcounter). The delay source can be selected from TIMEBASE (maximum 1.638ms) or A/D sampling clock (which can significantly extend the delay range). Suitable for applications that require avoiding triggering momentary interference.

Bus Master DMA and Data Transfer Optimization

For high-speed continuous data collection, software polling can result in extremely high CPU usage. The DAQ-20xx series supports Bus Mastering DMA and is equipped with Scatter/Gather linked list function (Figure 4-13), which solves the pain point of allocating large contiguous memory in operating systems such as Windows.

Implementation mechanism:

Multiple discontinuous memory blocks are concatenated through a DMA descriptor chain table, with each descriptor containing a PCI address, transfer size, and next descriptor pointer.

The maximum transmission capacity for non chain mode is 2M double words (8MB); There is no transmission length limit in chain mode, and it supports circular linked lists to achieve multi buffer continuous collection.

The hardware directly moves the data from the A/D FIFO to the user specified system memory without the need for CPU intervention, freeing up CPU resources for data processing and display.

Deployment suggestion:

Pre allocate larger DMA buffers (such as 64MB per channel) through the ACE tool of ADLINK MAPS Core to reduce interrupt frequency.

For long-term continuous recording, use Ping Pong mode in conjunction with linked list loops to avoid data loss.

Fine tuning of analog triggering and digital triggering

6.1 Five simulation triggering conditions

Manual figures 4-32 to 4-36 show five triggering conditions, all based on two comparison levels, Low_Threshold and High_Threshold (8-bit resolution):

Below Low: Triggered when the signal falls below a low threshold.

Above High: Triggered when the signal exceeds a high threshold.

Inside Region: Triggered when the signal is between high and low thresholds.

High Hysteresis: Triggered when the signal exceeds a high threshold, the low threshold determines the hysteresis hysteresis width (anti noise interference).

Low Hysteresis: Triggered when the signal falls below a low threshold, while a high threshold determines hysteresis hysteresis.