ADLINK PXES-2785 18 Slot Gen3 Chassis Deployment and Maintenance Guide

High: Forced full speed operation, at which point the speed curve varies depending on the Normal or Boost mode.

Recommended configuration combination:

Recommended settings for cooling requirements and ambient temperature

All modules ≤ 38W/slot 0~55 ° C Normal+Auto

Any module 38~50W/slot 0~55 ° C Boost+Auto

Any module 50~82W/slot 0~45 ° C Boost+High

Maximum ventilation ≤ 45 ° C High (mode on-demand)

Key clearances: Rear air outlet ≥ 101.6 mm (4 inches), side ≥ 44.45 mm (1.75 inches), bottom ≥ 17 mm (0.67 inches). All empty slots must be equipped with filling panels, and if there are empty slots in the adjacent left and right slots of high-power modules (>50W), wind resistance modules must also be installed to maintain directional airflow.

2.4 Hardware installation steps

System controller installation (Slot 1, highlighted in red):

Ensure that the CPU, memory, and storage of the controller are installed completely;

Press the module to eject the latch and push it in along the upper and lower guide rails;

Lift the latch to engage and tighten the front panel screws.

Peripheral module installation (Slot 2~18): Similar operation, note that the PXI-1 module can be installed in the mixed slots (7, 8, 9, 11, 12, 13), and the dedicated slots are only available for PXIe/CPCIe. Fill all empty slots after installation is complete.

Rack installation: remove the right handle and the left four rubber feet, fix the left and right mounting brackets with M4 screws (adjustable position), and then fix them with eight rack screws.

2.5 Power on and power-off

The chassis adopts C19 power inlet (16 A current capacity). Insert the power cord into the rear, press the front panel power button (if the Inhibit switch is in DEF mode), and the blue Power LED will light up. It is strictly prohibited to hot plug any module or cable, otherwise it may damage the device or cause data loss.

Backplane architecture and high-speed characteristics

3.1 PCIe Gen3 Link Capability

System slot to switch chip: 2-link x8 x16 Gen3, total bandwidth 24 GB/s;

All peripheral slots (including system timing slots when used as peripherals) independently support PCIe x8 Gen3, with a single slot bandwidth of 8 GB/s, and are not shared with each other. This design enables high-throughput modules such as multi-channel digitizers and vector signal transceivers to operate at full speed simultaneously.

3.2 Star Trigger (System Timing Slot 10)

Slot 10 provides one single ended star trigger (PXI_STAR) and three pairs of differential star triggers (PXIe-DSTAR A/B/C). The routing allocation is shown in Table 1-20 (for example, the PXI_STAR line in Slot 2 corresponds to number 7, Slot 3 corresponds to number 6, etc.). After installing a dedicated star trigger controller, precise synchronous triggering can be achieved. If this feature is not required, Slot 10 can be used as a regular x8 peripheral slot.

3.3 Three segment trigger bus and software bridging

18 slots are divided into three trigger bus segments:

Segment A: Plot 1-6

Segment B: Plot 7-12

Segment C: Slot 13-18

Each segment has 8 trigger lines, which are connected between segments through two bus buffers. Users can independently configure the bridging state of each trigger line through ChassisWatch or PXI-9 C++API, achieving 8 types of inter segment connection combinations and flexibly dividing trigger domains.

3.4 Priority of 10 MHz reference clock source

Automatic selection order:

Highest priority: PXI_CLK10-IN signal of system timing slot (Slot 10);

Secondary high: External 10 MHz clock input from the rear BNC;

Minimum: Built in oscillator on the backplane (accuracy ± 1 ppm).

When an external clock is present, the PLL automatically locks and synchronizes the 100 MHz differential clock to ensure that the entire chassis is in phase.

System monitoring and remote management

PXES-2785 provides two remote monitoring methods: SMBus (embedded controller through system slot) and Ethernet LAN port (rear RJ-45, default static IP 192.168.1.10/24). The ChassisWatch graphic tool supports two interfaces.

4.1 ChassisWatch Core Features

Status monitoring: Real time display of 8 backplane temperature sensors (T1~T8), 3 rear fan speeds, and all voltage rail readings;

Triggering bus routing: graphically configuring three-stage bus bridging, which can save/load templates;

Intelligent fan: target temperature setting (default 50 ° C, range 25~70 ° C), fan PWM curve similar to PXES-2780;

Threshold settings: adjustable voltage (default ± 5%), temperature (default 70 ° C), and fan speed (default 800 RPM);

Log and configuration: Record monitoring data, save/load threshold configurations.

4.2 Remote management of LAN web pages

Built in HTTP web service, no software installation required to access the chassis IP through a browser and view real-time voltage, temperature, and fan status. The IP settings (DHCP/static) can be modified in ChassisWatch. This feature greatly facilitates the monitoring needs of unmanned or remote laboratories.

4.3 Suppression/Voltage Monitoring DB-9 Interface

The rear DB-9 provides:

Voltage monitoring pins: 5VSB, 12V, 5V, 3.3V, -12V (each string has a 10k Ω current limiting resistor, which can be connected to a digital multimeter);