MOTOROLA CPCI-6020 CompactPCI Single Board Computer

BD_SEL # signal: controls whether the backplane power supply supplies power to the board.

HEALTHY # signal: Report to the backplane whether the power status of the board is normal.

Communication with remote HSC: Through dedicated signals on J3 (HSC-REQ #, HSC-GNT #, HSC-FLOAT, HSC-EJECT #), remote hot swappable controllers are allowed to request and take over control of the local CompactPCI bus, enabling the replacement of system controllers without interrupting service.

5. Debugging and Diagnosis:

PPCBug firmware: stored in Bank B Flash, it is a powerful command-line based debugging monitoring program and hardware diagnostic kit. It is responsible for power on initialization, hardware self-test, providing memory/register viewing and modification, breakpoint debugging, program download (via serial port or network), and starting the operating system.

Physical debugging interface: The 190 pin Mictor connector provides full speed trace access to the processor bus; The standard JTAG interface supports processor core debugging.

Firmware usage and system startup

After the system is powered on or reset, the initialization sequence of PPCBug firmware will be automatically executed, which includes MPU register setting, cache invalidation, hardware device (PCI bridge, memory controller, etc.) initialization, memory capacity detection, clock calibration, PCI device enumeration, etc. After completion, the onboard fault LED will turn off and the MCP820Bug>or PPC Bug>prompt will be displayed on the console (default connection to the front panel COM19600bps, 8N1).

Users can interact with the system through a variety of PPCBug commands:

System configuration command: CNFG is used to view and modify board information blocks (such as serial number, Ethernet address); ENV is used for detailed configuration of startup parameters, such as automatic boot switch, boot device sequence, network parameters, watchdog settings, etc.

Memory and I/O operation commands: MD/MM (display/modify memory), RD/RM (display/modify registers), PF (set port format).

Program debugging commands: GO (execute program), BR (set breakpoint), GT (run to temporary breakpoint), DS (disassemble).

Diagnostic command: Use the SD command to switch to the diagnostic directory and run integrity tests for specific hardware such as memory, UART, PCI bus, real-time clock, etc.

Boot commands: RB (boot from Flash), PBOOT (boot from disk), NAB (boot from network).

Special note: Extreme caution should be exercised when reprogramming Flash using commands such as PFLASH. Incorrect operations may erase Bank B Flash containing PPC bugs themselves, causing the board to fail to boot.

Application areas and compliance

CPCI-6020, with its powerful processing capabilities, rich I/O, high reliability, and modular design, is widely used in telecommunications infrastructure (such as base station controllers, media gateways), industrial automation, military embedded computing, and any field that requires robust, high-performance CompactPCI solutions.

This product is designed to comply with multiple international standards, including:

Safety standard: UL/EN/IEC/CSA 60950-1.

Electromagnetic compatibility: comply with FCC Part 15 Class A, EN 55022 Class A, CISPR 22, etc. (usually tested in compliance systems).

Environment and Reliability: Meets partial requirements of NEBS GR-63-CORE (Environment), GR-1089-CORE (EMC and Safety), as well as ETSI EN 300 019 series standards.

Environmental Directive: Compliant with the European Union's Directive on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment (RoHS).