MOTOROLA CPCI-6020 CompactPCI Single Board Computer

Motorola CPCI-6020 CompactPCI Single Board Computer

The Motorola CPCI-6020 (formerly known as MCP820) is a high-performance 6U Eurocard specification CompactPCI single board computer (SBC) designed specifically for demanding embedded communication and industrial control applications. Its core is equipped with AltiVec ™ The Freescale MPC7410 Reduced Instruction Set (RISC) processor, with a clock speed of up to 500 MHz, provides powerful power for algorithm intensive computing tasks. This manual aims to provide engineers and technicians with comprehensive guidance from unboxing inspection, hardware configuration, system installation to deep functional understanding, ensuring that the board can operate stably and efficiently in the target system.

Product Overview and Core Features

The CPCI-6020 design follows the CompactPCI (PICMG 2.0 R2.1) standard and can serve as a system slot controller, providing system clock and arbitration for the backplane. Its modular design allows users to flexibly expand by adding various daughter boards.

The core hardware features include:

Processor system: MPC7410 processor based on PowerPC architecture, with an external 2MB burst SRAM L2 cache, supporting bus parity check.

Memory system: No onboard memory, supports up to 2GB of ECC (Error Correction Code) protection SDRAM through two independent RAM500 memory expansion sub board interfaces. Each RAM500 module can have a capacity of 128MB, 256MB, or 512MB.

Storage: Provides two types of Flash memory: 32MB (Bank A, onboard) and 1MB (Bank B, socket type). Bank B pre installs PPC bug debugging and diagnostic firmware. Simultaneously equipped with a CompactFlash Type I/II slot, connected via EIDE interface.

PCI architecture: Adopting dual Harrier system memory controllers/PCI host bridge application specific integrated circuits (ASICs), forming two independent PCI bus layers (PCI Bus A and B). PCI Bus A operates at 33MHz and connects most of the onboard I/O and CompactPCI bridges; PCI Bus B can run at 33MHz or 66MHz depending on the capabilities of the installed PMC module.

Rich I/O interfaces:

Network: Two 10BaseT/100BaseTX Ethernet controllers based on Intel 825511T. Usually, the main channel is connected to the front panel RJ-45, and the secondary channel is led out through the rear I/O connector (J5). Routing can be adjusted through customized options.

Serial communication: Two 16550 compatible asynchronous serial ports (UART), two high-speed serial ports that can be configured as synchronous/asynchronous through Zilog ESCC controller.

USB: Four USB 1.1/2.0 host ports (NEC µ PD720101 controller), two of which are located on the front panel and two are routed to the rear I/O.

Expansion interface: A 32/64 bit PMC (PCI Mezzanine Card) slot that supports front and rear I/O. A dedicated Rear Transition Module (RTM) - CPCI-6020-MCPTM-01, used to convert user I/O signals from CompactPCI J3 and J5 connectors into actual connectors on the rear panel (such as EIDE, keyboard/mouse, serial port, Ethernet, etc.).

Other: In the 5E model variant, PS/2 keyboard/mouse interface, floppy disk controller, and speaker output are also supported.

High availability and hot plugging: Supports CompactPCI hot plugging specification (PICMG 2.1) and has Motorola high availability (HA) architecture extension function, supports hot plugging of system slots, and ensures the continuous operation of critical mission systems.

Debugging support: Provides a 190 pin Mictor debugging connector for accessing the processor bus, as well as standard processor JTAG interfaces and RISCWatch heads.

Detailed explanation of hardware installation and configuration

Successful deployment begins with proper hardware preparation. The installation of CPCI-6020 is a systematic process that requires strict adherence to ESD protection and mechanical safety regulations.

1. Unpacking and Inspection:

After receiving the board, it is necessary to immediately inspect the transportation packaging and the board itself for any physical damage, and verify all components that should be delivered. Before handling the board, it is necessary to ensure that the working environment has electrostatic discharge (ESD) protection measures and wear a grounding wristband.

2. Key jumper settings:

Multiple user configurable jumpers are provided on the board to define startup and behavior modes. These jumpers are mainly located on the side of the board and need to be set correctly before installing any daughter board.

J24- Flash Storage Selection: Select which Flash storage to boot the system from. Short circuit 1-2 pins and select 32MB onboard Flash (Bank A); Short circuit 2-3 pins and select 1MB socket type Flash (Bank B, containing PPCBug, factory default).

J22- Harrier Power On Configuration Head: An 8-pin connector that can set the universal power on status bit (PUST [3:0]) of Harrier ASIC by short circuiting different pins, allowing software to read and identify specific configurations.

J21- PMC 66 MHz disabled: Short circuiting this jumper will force PCI Bus B to run at 33MHz, even if the installed PMC module supports 66MHz. This can prevent the secondary Ethernet controller on PCI Bus B from being disabled due to bus acceleration to 66MHz.