ADLINK ACL-7122 Digital I/O Card Installation and Programming

ADLINK ACL-7122 144 bit Digital I/O Card Installation and Programming Practical Guide

In industrial automation production lines, old ISA bus equipment is still widely used in CNC machine tools, semiconductor test benches, and power monitoring systems. The ACL-7122 144 bit parallel digital I/O card launched by ADLINK has become the preferred choice for many system integrators due to its six sets of high-density analog 8255 PPI channels and OPTO-22 compatible interface. As the original factory gradually stops production, how to correctly deploy, configure, and program this card has become a practical challenge for maintenance engineers. This article is based on the official technical manual, providing a complete set of operating instructions from hardware installation, address jumpers, interrupt settings to C language programming examples to help you extend device life in existing systems.

Product positioning and core features

ACL-7122 is a half size (183mm × 111mm) ISA expansion card that provides 144 TTL/DTL compatible digital I/O lines, divided into 6 channels, each channel simulating an Intel 8255 programmable peripheral interface (PPI), including PA, PB 8-bit ports and PC ports (divided into high 4 bits and low 4 bits). Its main features include:

High driving capability: The PA/PB port outputs a minimum high level of 2.4V and a current of 24mA; the PC port also has a current of 24mA and can directly drive relays or optocouplers.

Flexible Interrupt: Each channel's PC0 (rising edge trigger) and PC3 (falling edge trigger) can generate hardware interrupts, supporting IRQ 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, and supporting multi card sharing of the same interrupt (tri state output).

Output read back: Even if the port is set to output, the current output latch status can still be read for easy fault diagnosis.

Fully compatible with Advantech PCL-722, it can directly replace old models.

Data transmission rate: typical 300KB/s, up to 500KB/s, meeting the requirements of high-speed digital control.

Open box inspection and anti-static treatment

The kit includes ACL-7122 card and user manual (3rd edition, 1997). After receiving the goods, please check the PCB for any physical damage, especially paying attention to whether the 50 pin IDC connector pins are bent. Due to the sensitivity of CMOS devices on the card to static electricity, it is essential to:

On the grounding anti-static pad;

Wear an anti-static wrist strap and share the ground with the mat;

After removing from the anti-static bag, hold only the edge of the card to avoid touching the gold fingers and IC.

It is recommended to press all plug-in ICs (such as 8255 compatible chips) to ensure that they are not loose during transportation.

Jumper and DIP switch configuration

There is a SW1 (5-bit DIP switch) on the card for base address setting, JP0~JP5 for channel interrupt enable, JP6 for global IRQ selection, and JP7 for selecting 144 bit or 96 bit modes.

1. I/O mode selection (JP7)

144 bit mode (default): occupies 32 consecutive I/O ports and provides all 6 channels (CH0~CH5).

96 bit mode: occupying only 16 ports, disabling CH4 and CH5, suitable for systems with tight address space.

Maintain 144 bit mode unless conflicting with other card addresses.

2. Base address setting (SW1)

The base address must be within the range of 200h~3F8h and cannot conflict with the system reserved address (such as COM/LPT). The manual provides a detailed truth table. Taking the example of setting the base address to 2C0h:

Map address lines A9~A4 to DIP1~DIP6, where A9 is fixed at 1 (OFF) and hardware forces A3~A0 to 0.

The binary value of 2C0h is 10-11 million, which means A9=1, A8=0, A7=1, A6=1, A5=0, A4=0, A3~A0=0.

DIP switch status: A9（DIP1）=OFF(1)，A8（DIP2）=ON(0)，A7（DIP3）=OFF(1)，A6（DIP4）=OFF(1)，A5（DIP5）=ON(0)，A4（DIP6） In 144 bit mode, it has no effect (Don't care) and can remain ON.

Table 2.2 of the manual lists switch combinations for commonly used addresses such as 200h, 2C0h, 3A0h, etc. The default factory setting is 2C0h.

Note: A4 is invalid in 144 bit mode because port 32 requires A4 to be 0, but the switch position can be ignored; The 96 bit mode requires precise definition of A4 according to Table 2.3.

3. Interrupt settings (JP6 and JP0~JP5)

JP6: Select global IRQ, a total of 11 options available, default IRQ15 (usually idle). If there is a conflict with other devices, it can be changed to IRQ9, 10, etc. Insert the jumper cap into the corresponding pin pair.

JP0~JP5: Enable interrupts corresponding to CHO~CH5. Each jumper has three states:

D (Disabled): This channel does not generate interrupts.

E (Enable): Enable interrupt, the triggering edge is determined by the combination of PC0 and PC3 (see below).

P (Programmable): Programmable interrupt, requires PC4 to be pulled down simultaneously to activate the interrupt, allowing software to mask the interrupt.

Trigger edge logic:

In E-mode: PC0 is triggered by the rising edge (Low → High), and PC3 is triggered by the falling edge (High → Low). If PC0 is High and there is no jump, it will not be triggered.

In P mode: except for the above edge conditions, PC4 must be Low to allow interrupt output; If PC4=High, all interrupts are prohibited.