ADLINK ACL-7122 Digital I/O Card Installation and Programming

This design allows for software shutdown interrupts or cascading multiple interrupt sources through PC4.

Definition of connector pins and external wiring

The six 50 pin IDC male heads (CHO~CH5) on the card are arranged with OPTO-22 standard pins and can be directly connected to ADLINK's TB-24R (24 relay outputs), TB-24P (24 optocoupler inputs), or TB-16P8R (16 inputs+8 outputs) terminal boards. The PA, PB, and PC of each channel each occupy 8 bits, among which the high 4 bits (PC4~PC7) and low 4 bits (PC0~PC3) of the PC can be independently set for input/output.

Typical connection method:

Control external relays: Set PA/PB as the output, connect TB-24R through a ribbon cable, and drive one relay coil for each output position.

Read limit switch: Set PC or PA as input, connect TB-24P, and isolate external 24V signal with optocoupler.

Attention: All I/O are TTL level (high ≥ 2.0V, low ≤ 0.8V). If high voltage/high current loads need to be driven, they must be isolated through OPTO-22 module or relay board to avoid damaging the card.

Register Structure and Programming Fundamentals

The I/O mapping of ACL-7122 is based on four registers (PA, PB, PC, control word) per channel, with the base address set to B. Therefore:

CH0: B+0 (PA), B+1 (PB), B+2 (PC), B+3 (CW)

CH1: B+4~B+7

CH2: B+8~B+11

CH3: B+12~B+15

CH4: B+16~B+19

CH5: B+20~B+23

Control word format (written to CW register):

D7=1 (mode setting flag), D6~D5=00 (mode 0), D4=port A direction (0=output, 1=input), D3=PC high 4 bit direction (0=output, 1=input), D2=port B direction, D1=PC low 4 bit direction, D0 unused (usually 0).

For example, set all ports of CH0 as output: control word=1000 0000b=0x80.

Set the PA input, PB output, PC input, and PC output for CH1: D4=1, D3=1, D2=0, D1=0 → Binary 1 001 1 000 0=0x98.

Power on default: All ports automatically enter input mode, and the output latch is a random value. If output is required, the control word must be written to define the direction first, and then the data must be written to the corresponding port.

Output Read Back: Even if set as output, executing inportb (B+PA) can still read the current latch value, making it easier to verify program logic.

Detailed Analysis of Interrupt Programming

Using interrupts requires three steps:

Hardware settings: Select IRQ through JP6 and set JPx to E or P mode.

Software initialization: Write the appropriate I/O direction to the control word of the corresponding channel (note that PC0/PC3 must be inputs to receive external triggers, as they are interrupt source pins).

Clear interrupt status and allow interrupt: The manual provides a "false read" technique: first write an index to the control word register of the channel (i.e. base address+3,+7,...), and then read once from the PC port of this channel to clear the suspended interrupt and re enable it. Example code:

outportb(BASE+3, 0x00); //Point to CH0 CW (in fact, just write any CW address)

dummy = inportb(BASE+2); //Read PC0, clear interrupt

This operation will reset the interrupt trigger logic, enabling subsequent edge detection.

Writing ISR: Under DOS or Windows 3.1/95, interrupts can be mounted using the setvect() function of d_dos_getvect/d_dos_detvect or Borland C. In the service program, it is necessary to read the corresponding PC port to determine the interrupt source (PC0 or PC3 level), but please note that the input is not latched, and the order cannot be determined. Only the current state can be recognized.

Self triggering test: The manual provides an example program that generates interrupts through software simulation - by applying a jump to the PC0 or PC3 pin of a certain channel (by writing to the PC port), the interrupt can be triggered for debugging.

Interrupt sharing: Due to the output being in three states, multiple ACL-7122s can share the same IRQ. ISR needs to poll the status of each card to determine which card has generated an interrupt.

Common troubleshooting

Based on the manual and on-site experience, the following is compiled:

Possible causes and solutions for the fault phenomenon

The system is unable to recognize card base address conflicts or check for SW1 settings beyond the range. Refer to Appendix A to confirm unoccupied addresses (such as 2F8h as COM2, 3F8h as COM1, etc.)

If there is no level change in the output port, forget to write the control word or if the control word is incorrect, make sure to write CW first and then write the data; Check D7=1, correct direction position

Interrupt does not trigger JPx not set to E/P, or IRQ is blocked to confirm JPx jumper; Check if the IRQ in the system BIOS is assigned to ISA instead of PCI; Viewing the masking register with inportb (0x21) in DOS

Interrupt triggered multiple times or randomly triggered but not cleared correctly (false read not executed). In each ISR, a read operation must be performed on the PC port to clear the edge detection flag

When multi card sharing is interrupted, the response is abnormal. ISR does not poll all cards. In ISR, read the PC ports of each card in sequence to determine which one has changed

Insufficient high-level output driver, unused buffer or heavy load PA/PB. The minimum high-level is 2.4V and the current is 24mA. If the load is too large, a driving transistor needs to be added