ADLINK PCI-9812/10 high-speed synchronous acquisition card

Deep technical analysis and engineering application of ADLINK PCI-9812/10 20MHz synchronous sampling data acquisition card

Introduction: The core position of high-speed synchronous sampling in complex signal processing

In applications such as radar, sonar, medical imaging (ultrasound, gamma cameras), non-destructive testing, and communication baseband signal analysis, the amplitude, phase, and spectral information of signals are crucial. These applications typically require multiple channels to simultaneously collect signals at extremely high sampling rates for subsequent complex operations such as FFT, digital filtering, and correlation detection. Traditional multiplexing acquisition cards cannot meet the requirements of phase sensitive measurements due to time skew between channels.

The Linghua PCI-9812/10 was born to overcome this challenge. Its biggest feature is that each of the four channels is equipped with an independent A/D converter, which can achieve true synchronous sampling, and the sampling rate can reach up to 20 MS/s (single channel) or 5 MS/s per channel (four channels simultaneously). This card adopts a 32-bit PCI bus, supports bus master DMA, and directly transfers data to the host memory, greatly reducing the burden on the CPU. Its flexible triggering mechanism and multiple clock sources (internal/external sine/external square wave) enable precise synchronization with external systems, making it suitable for various complex testing environments.

Hardware architecture and core specifications

2.1 Analog input channel

Number of channels: 4 single ended inputs (BNC interface, J1~J4）。

Resolution: PCI-9812 is 12 bits, PCI-9810 is 10 bits (with no missing codes).

Input range: ± 1V or ± 5V (factory default ± 1V, 50 Ω input impedance) can be selected through the solder pads on the board.

Input impedance: It can be configured as 50 Ω (low impedance, suitable for high-frequency signals), 1.25k Ω, or 15M Ω (high impedance) by combining pads (COLO and CO5V). Default 50 Ω is used for matching 50 Ω coaxial cables. Attention: If configured with high impedance (15M Ω) and large input bias current (about 15mA), a low impedance signal source must be connected to provide a return path, otherwise it will damage the A/D converter.

2.2 Clock System

Internal clock: The onboard 40MHz crystal oscillator generates a sampling clock through a 16 bit even frequency divider (2~1024).

External clock: supports two types of external clock sources——

Sine wave clock (J5 BNC, 50 Ω AC coupling, 2Vpp input).

Square wave clock (JP1 pin 1, TTL level, 50 Ω DC coupling).

Regardless of the type of clock, it passes through a frequency divider, so the external clock frequency is at least twice the required sampling rate (with a minimum division factor of 2).

2.3 Trigger System

Trigger source: software trigger (calling DMA start function), external analog trigger (any analog input channel can set trigger level through DAC) and external digital trigger (JP1 pin 3, TTL edge).

Trigger mode:

Software trigger: Directly initiate data collection.

Post trigger: Start collecting a specified number of samples after the triggering event occurs.

Pre trigger: Collection starts before triggering and stops when a triggering event occurs.

Middle trigger: Collection is performed before and after triggering, and the number of samples after triggering is set by the post trigger counter.

Delay trigger: After triggering an event, a specified number of sampling clocks are delayed before collection.

2.4 FIFO and Data Flow

The total capacity of the onboard FIFO is 32K words (16 bit width). When 4 channels are sampled simultaneously, the FIFO depth of each channel is 8K samples; When using only 2 channels (0 and 1), each channel has 16K samples; When only one channel is used, all 32K samples belong to that channel.

The data is transferred to the host memory through the bus master DMA without the need for CPU intervention. The PCI controller (AMCC S5933) is responsible for handling bus arbitration and burst transmission.

Register programming and underlying control

PCI-9812/10 occupies 9 32-bit I/O addresses (Base+0 to Base+0x20), and all accesses must be 32-bit wide. The key registers include:

Offset write function and read function

Base+0 ADC channel enable (CHO~CH3) -

Base+4 clock division factor (2~1024, even) -

Base+8 trigger mode selection -

Base+C trigger level (8-bit DAC) -

Base+10 trigger source and polarity -

Trigger counter value after Base+14-

Base+18 FIFO control (clear FIFO, clear trigger flag) FIFO status (half full, empty, overflow, trigger detection, etc.)

Base+1C acquisition enable -

Base+20 clock source selection and frequency labeling -

Channel enablement rule: Hardware only allows three valid channel combinations - CH0 only, CH0+CH1, and all four channels. Not supporting combinations such as CHO+CH2 or only CH2+CH3, as the internal hardware scanning sequence is fixed (0 → 1 → 2 → 3 cycles).

Divider: The written value must be even, with a minimum of 2. The internal clock source is 40MHz, so the maximum sampling rate is 20MHz; The frequency of the external clock source is not limited (but it must meet the requirement of ≤ 20MHz after frequency division).