ADLINK PCI-9812/10 high-speed synchronous acquisition card

Trigger detection: When simulating a trigger, the onboard DAC generates a comparison voltage, which is compared with the input signal, and the comparator output edge is used as the trigger event. The triggering delay is about 350ns, which has a slight impact on high-speed acquisition and needs to be considered in the timing design.

Working mode and data throughput limitations

4.1 Synchronous Sampling and Multi Card Synchronization

Due to the independent ADC of each channel, the theoretical synchronization deviation of the four channels in the same card is extremely small (clock edges arrive simultaneously). But when multiple cards need to be synchronized, even if the same external clock source is used, there may be a phase shift of half a sampling clock cycle due to the internal frequency divider (÷ 2) of each card. The manual clearly states that full synchronization of multiple cards cannot be achieved unless the user designs an external clock allocation and carefully calibrates the delay.

4.2 Continuous acquisition length limit

This is the most critical engineering constraint in high-speed data acquisition. Total data throughput=sampling rate x number of channels x 2 bytes. For example, at 4 channels and 20MS/s, the total throughput is 160MB/s, far exceeding the theoretical peak of 132MB/s and the actual effective bandwidth (usually<100MB/s) of the PCI bus (32-bit/33MHz). Therefore:

If the total throughput rate is ≤ PCI effective bandwidth, DMA can be used for continuous transfer, with a maximum data volume of 64MB (limited by the PCI controller), which is specifically limited by the available continuous memory of the host.

If the total throughput rate is greater than the PCI bandwidth, the data can only rely on FIFO cache, and the maximum number of continuously collected samples is limited by the FIFO capacity -16K samples per channel for 2 channels and 8K samples per channel for 4 channels. If exceeded, FIFO overflow occurs (status bit FIFOOR set).

Section 5.5 of the manual provides detailed decision-making steps and emphasizes that at high speeds, CPU processing power and hard disk write speed can also become bottlenecks. It is recommended to use double buffering technology to achieve infinite continuous acquisition (but software cooperation is required, and processing speed must keep up).

C/C++software libraries and drivers

5.1 Overview of Library Functions

Linghua provides Borland C++library for DOS and DLL (function name prefix with W_) for Windows 95/98. The core functions include:

_9812Initialize: Initialize the card, return the base address, IRQ, and PCI master status.

_9812_Set_Clk_Src/_9812_Set_Clk-Rate: Set the clock source and division factor.

_9812_Set_Trig: Configure trigger mode, source, polarity, level, and post trigger count value.

_9812_AD_DMA_Start: Start DMA acquisition, specify channel combination (1/2/4), total number of samples, and buffer address (DOS) or memory handle (Windows).

_9812_AD_DMA_Status: Query the collection progress and status (in progress, waiting for trigger, delayed, completed).

_9812_AD_DMA_Stop: Terminate collection prematurely and return the number of transferred samples.

Windows specific functions: W_9812_ Alloc_DMA_Sem (allocate contiguous physical memory), W_9812_Sree_SMA_Sem, and W_9812_Get_Sample (for accessing data in languages such as VB).

5.2 Data Format

Each 16 bit data sample contains 12 (or 10) bits of ADC data (MSB aligned), 3 bits of universal digital input (DI0~DI2), and 1 bit of trigger detection flag. The Least Significant Bit (LSB) has 4 zeros in 12 bit mode and 6 zeros in 10 bit mode, and the software needs to perform truncation or shift processing.

5.3 Programming Process

Typical collection process:

_9812Initialize obtains resources.

_9812_Set_Clk_Src and _9812_Set_Clk-Rate set the clock.

_9812_Set_Trig configuration triggered.

Allocate memory for (Windows) W_9812_ Alloc_DMA_Sem.

_9812_AD_DMA_Start starts collection (starts immediately in software triggered mode; waits for triggering in other modes).

Loop call _9812_daD_DMA_Status to monitor the status until completion.

Process data and call _9812_AD_DMA_Stop (if necessary).

Release resources (_9812_Close and W_9812_Sree_SMA_Sem).

Calibration and debugging tools

6.1 Hardware Calibration

Onboard 8 adjustable potentiometers (VR1~VR8), corresponding to bias and full-scale calibration of four channels respectively. Factory calibrated, it is recommended to recalibrate every 3 months when there are significant environmental changes. Calibration requires a high-precision voltage source (± 1V or ± 5V), guided by calibration software (9812til. exe) to gradually adjust the corresponding VR, so that the read value is within the error range.

6.2 Practical Tools (9812til. exe)

9812til under DOS provides three main functions:

System configuration: Display card number, base address, IRQ, and PCI master status.

Calibration: A graphical interface that indicates which VR should be adjusted for each step and displays the ADC sampling values in real-time.

Functional testing: Trigger mode, polarity, trigger level, channel number, and post trigger count value can be set to display the collected waveform in a graphical manner, helping users intuitively verify trigger behavior and sampling effect.