ADLINK PCIe-7256 Industrial I/O Card Interruption and Relay

ADLINK PCIe-7256 Industrial I/O Card Interruption and Relay Status Management

In the field of industrial automation and process control, digital input/output (DIO) cards play a critical role in connecting on-site signals and control systems. When it comes to high reliability switch control, real-time capture of state changes, and long-life actuator driving, traditional non latch relays and polling input acquisition often struggle to balance power consumption, response speed, and system complexity. ADLINK PCIe-7256, as a 16 channel latch relay output and 16 channel optocoupler isolated digital input card, provides engineers with a low-power and high real-time solution through hardware level Change of State (COS) interrupt mechanism and dual coil latch relay design. This article will deeply analyze the architecture characteristics, register programming model, interrupt processing flow of the card, and combine it with practical application scenarios to explain how to use its unique functions to build a stable and reliable industrial monitoring and control system.

Latch relay output: perfect balance between power consumption and state maintenance

Traditional electromagnetic relays require continuous power supply after operation to maintain the contact state, which not only increases system power consumption but also affects their lifespan due to long-term coil heating. PCIe-7256 adopts a dual coil latch relay (DPDT, Form C), and its SET and RESET are triggered by independent pulses. Once the relay is activated, even if the drive signal is removed, the mechanical contacts remain in their current state until a reverse pulse is received. This feature brings two core advantages:

Power off state memory: When the system unexpectedly loses power, the state of all output channels is physically locked, and after re powering on, the previous control logic can be restored without additional initialization, especially suitable for safety interlock and valve holding scenarios.

Extremely low steady-state power consumption: only consumes current at the moment of switching (typical value)+ 12V@141mA Simultaneously activate all channels, with zero power consumption of the coil in steady state, significantly reducing the thermal load on the chassis.

The SET/RESET status of each channel is visually indicated by onboard LEDs, and the JP3/JP4 interfaces on the board support external LED arrays (connected in series with 330 Ω current limiting resistors, compatible with LEDs with Vf<2V), which can extend the status indication to the cabinet panel for easy on-site inspection. In terms of contact parameters, the rated load is 125V AC/0.5A or 30V DC/1A, which meets the majority of industrial ON/OFF control requirements; The mechanical lifespan is up to 2 × 10 ⁵ times (resistive load), and the release/pull in time is only 3ms, which is sufficient to cope with high-speed switch scenarios.

Optocoupler isolated digital input: anti-interference and flexible filtering

The 16 channel digital input adopts PC-3H4 optocoupler to achieve 2500Vrms channel system isolation, with a rated input current of 10mA (maximum 50mA), a logic high level threshold of 5-24V (AC or DC), a low level of 0-2V, and an input impedance of 4.7k Ω. Field signals, whether from proximity switches, limit switches, or 24V DC sensors, can be directly connected without additional level conversion.

It is worth noting that each input channel can independently select AC filtering or non AC filtering mode through onboard jumpers (JP1 corresponds to DI0~DI7, JP2 corresponds to DI8~DI15). The default setting is non AC filtering (DC coupling), in which case the input signal responds directly; When the jumper is placed in the AC filtering position, the built-in RC filter can effectively suppress power frequency interference and contact jitter, especially suitable for AC signal sources or long-distance transmission scenarios. This hardware configurability avoids the delay uncertainty caused by software filtering, allowing engineers to flexibly choose between real-time performance and noise resistance.

Change of State (COS) interrupt: Say goodbye to polling, respond in real-time

Traditional digital I/O cards require the CPU to periodically read input ports to detect status changes, which not only occupies bus bandwidth but also has response delays that depend on polling cycles. PCIe-7256 has built-in COS detection logic, and the state transition (rising edge or falling edge) of each input channel can trigger hardware interrupts, automatically latch the current input data, and notify the CPU for processing. This mechanism frees up the CPU, especially suitable for limit switches, emergency stop buttons, or pulse counting scenarios that require quick response.

Detailed explanation of COS workflow

Enable COS channel: Write 1 to the COS Setup register (Base+0x06, write) to enable the COS interrupt for the corresponding channel. This register is 16 bits, with each bit corresponding to one DI.

Interrupt trigger: When the enable channel undergoes a 0 → 1 or 1 → 0 change, the hardware sets the interrupt request, and at the same time, the COS Latch register (Base+0x06, read) captures a snapshot of the current 16 input levels to prevent the state from changing when the main loop reads.

Interrupt handling: After the CPU responds to the IRQ, it reads the COS Latch register to obtain the changed input value and executes the corresponding logic (such as alarm, status update, actuator linkage).

Clear Interrupt: Write 1 to the COS_CLR bit of Interrupt Control Register (Base+0x08) to clear the interrupt request and automatically reset the COS Latch register, allowing the next change to continue triggering.

Note that COS Latch data only remains valid until the interrupt is cleared, and automatically resets to zero after clearing. Therefore, the service routine must complete data reading before clearing the interrupt.

Dual interrupt source mode: Channel 0/1 rising edge trigger

In addition to COS mode, PCIe-7256 also supports rising edge interrupts based on DI channel 0 and/or channel 1 (mode 2). In this mode, interrupts are only generated when the input signal jumps from low to high, making it suitable for capturing positive edge pulses (such as encoder zero position signals or start commands). Two interrupt sources can be enabled separately or simultaneously, and the interrupt sources are distinguished by the interrupt status register (Base+0x08, read).

Important constraint: COS mode and channel 0/1 rising edge mode share the same interrupt signal line and cannot be enabled simultaneously. If the corresponding enable bits are set simultaneously, the hardware will enter an undefined state (clearly marked as "Forbidden" in the manual). Therefore, when programming, it is necessary to ensure:

If COS is enabled (Bit8=1), Bit9 and Bit10 must be 0.

If Ch0 (Bit9=1) or Ch1 (Bit10=1) is enabled, Bit8 must be 0.

The read and write properties of the interrupt control register (Base+0x08) are different: write operations are used to enable/clear interrupts, while read operations are used to query interrupt and enable states. The clear operation is completed by writing "1" to the corresponding clear bit (Bit0~Bit2), which will not affect the enable configuration.

Key points of register mapping and low-level programming

All registers of PCIe-7256 are 16 bits wide and must be accessed using 16 bit I/O instructions. The base address is automatically assigned by the PCIe plug and play system and does not require manual setting. The register mapping is shown in the following table (offset address relative to Base):

Offset address write operation read operation

0x00 relay output CHO~7 control undefined (not supported)

0x02 Relay output CH8~15 Control relay output status feedback (CHO~15)

0x04 undefined isolated digital input status (CHO~15)

0x06 COS Setup Register COS Latch Register

0x08 Interrupt Control Register Interrupt Status Register

Relay control coding details

Each latch relay is determined by two control bits (S and R):

SET (1,0): The normally open (NO) contact is closed, the normally closed (NC) contact is open, and the corresponding output state is "1".

RESET (0,1): NO is open, NC is closed, and the corresponding output state is "0".

Prohibition of (1,1) or (0,0): The former may lead to uncertain states, while the latter has no effect and should be avoided.

Therefore, in actual programming, the 16 bit output data needs to be mapped into a 32-bit control word, with the high bit being the SET bit and the low bit being the RESET bit. But the official library function _7256-DO simplifies this process by simply passing in 16 bit data (bit=1 represents SET, bit=0 represents RESET), and the library automatically converts it into a dual coil pulse sequence. However, if performing direct operations on the underlying registers, it is necessary to follow the two bit encoding rule.

Difference between input register and read back register

Isolation input register (Base+0x04): reflects the actual level of the current DI pin (after optocoupler and filtering), updated in real time.

COS Latch register (Base+0x06): an input snapshot that freezes only when a COS interrupt is triggered, used to confirm the state at the time of the interrupt.

Relay read back register (Base+0x02): reads the actual state of the current relay contact (SET=1, RESET=0), which is consistent with the written value (unless there is a mechanical fault).

Board ID and Multi Card Management

When multiple PCIe-7256 are installed in the same system, assign a unique Board ID (0-15) to each card through the S1 DIP switch (4 bits). This ID is not related to the base address, but serves as a logical handle when calling library functions, ensuring that the software can accurately address specific cards. Set the rules as shown in Table 2-1 (binary encoding, 1=ON, 0=OFF), for example, ID=0 corresponds to all switches being OFF, and ID=15 corresponds to all switches being ON. The initialization function _7256Initialize will automatically detect all cards and return the number of cards that exist, and subsequent functions will be distinguished by the boardID parameter.

Software Drivers and Development Suggestions

ADLINK provides the PCIS-DASK SDK (supporting Windows 7/8.1), which encapsulates all underlying register operations, including DLLs and C/C++libraries. Appendix A lists the main functions:

_7256Initialize: Must be called first to complete PCIe resource allocation and board enumeration.

_7256-DO/_7256-DO-Read_Sack: Relay write/read back.

_7256-DI: Read the current input status.

_7256_SOS_Channel: Set the COS enable mask.

_7256-IND_Control: Select the interrupt source (COS or Ch0/Ch1 rising edge).

_7256_SLR_SRQ: Clear interrupt request (corresponding clear bit needs to be passed in).

_7256_SOS_Latch: Read COS latch data.

_7256_gET_SRQ_Status: Query the current interrupt source status.

Attention should be paid to the design of interrupt service routines (ISR) during development: since interrupt clearing and latch clearing are performed synchronously, it is necessary to read the latch data first and then clear the interrupt, otherwise the data will be lost. In addition, if choosing Ch0/Ch1 rising edge mode, it is necessary to ensure that the input signal is not jitter. If necessary, a Schmitt trigger can be added externally or hardware filtering jumper can be used.

Typical application scenarios and selection considerations

Scenario 1: High voltage relay array control

In semiconductor testing equipment, it is necessary to switch multiple high-voltage signals. The latch relay of PCIe-7256 can maintain its state for a long time without generating heat, and each channel has independent LED indicators and external LED interfaces for maintenance personnel to quickly locate abnormal channels. 16 way double pole double throw contacts can simultaneously control two independent load circuits, saving the number of boards.

Scenario 2: Safety limit monitoring system

The status changes of multiple limit switches on the automated production line require quick response. After enabling COS interrupts, any switch action triggers CPU processing, and the delay depends only on the interrupt response time (microsecond level), which is much better than the millisecond level delay of software polling. Optocoupler isolation effectively prevents common ground interference caused by motor start stop, ensuring signal accuracy.

Scenario 3: Remote Terminal Unit (RTU) simulation

In the SCADA system, PCIe-7256 can be used as a PC based RTU to collect remote signals through DI and output remote control commands through relays. After a power outage, the relay maintains its state and automatically recovers upon restoration, meeting the strict requirements of the power system for "maintaining the final state".

Comparative advantage with competitors

Compared to ordinary non latch relay cards, PCIe-7256 has significant advantages in power-off holding and low power consumption; Compared to a simple input card, its COS interrupt reduces CPU burden and improves system throughput. Although the single card price is slightly higher, in situations where high reliability and fast response are required, the overall cost of this solution (eliminating external holding circuits and high-speed polling overhead) is more competitive.

Installation and configuration precautions

Anti static treatment: Before operation, be sure to wear a grounding wristband and and perform it on an anti-static workbench.

Driver priority: The PCIS-DASK driver must be installed before inserting the hardware to avoid misidentification by the operating system.

Jumper setting: Pre set the filtering selection for JP1/JP2 based on the input signal type (DC/AC, with or without contact jitter). The factory default is non AC filtering. If connected to AC 24V or mechanical contacts, it is recommended to enable filtering.

External LED connection: Ensure that the forward voltage drop of the LED is below 2V and the polarity is correct, otherwise it may not light up or be damaged. The onboard 330 Ω current limiting resistor has been integrated and does not require external string connection.

Power margin: When all relays are closed simultaneously, the maximum current of+12V reaches 500mA, and the maximum current of+3.3V is 45mA. It is necessary to ensure sufficient power supply.

Troubleshooting and Common Problems

Problem 1: Relay cannot be set/reset

Check if the driver is loaded and if the register is written correctly (prohibit writing (1,1)).

Confirm that the+5V relay power supply is normal (powered by onboard PCIe, no external required).

If the read back value does not match the write, it may cause mechanical jamming of the relay, and multiple reset/set pulses can be attempted.

Problem 2: COS interrupt not triggered

Confirm that the COS Setup register is correctly written (corresponding to bit 1).

Check if the interrupt control register has enabled Ch0/Ch1 mode incorrectly (the two are mutually exclusive).

Confirm whether the amplitude of the input signal change meets the logic high and low levels (needs to cross the threshold).

Read the interrupt status register. If COS Int_Status remains 0, it may indicate that the interrupt is not enabled or has been cleared.

Problem 3: The system cannot recognize multiple cards

Check if each card's Board ID is duplicated (must be unique).

Ensure sufficient power supply to PCIe slots, as some older motherboards may not provide sufficient power.

Run _7256Initialize to check the number of cards returned. If it is less than the actual number, check the PCIe resource allocation in the BIOS.