Remote Control Application and Troubleshooting of ADLINK PCIe-8560/PXI-8565 Expansion Kit

In automated testing systems, military aerospace equipment, and high-density data acquisition applications, the PXI platform has become the industry standard due to its modularity, high bandwidth, and robust structure. However, PXI chassis typically require collaboration with host controllers (such as embedded controllers or remote PCs), and traditional solutions are limited by the PCI bus distance (usually not exceeding 0.3 meters), resulting in the host having to be close to the object being tested, which is extremely inconvenient in high temperature, vibration, or narrow space environments. The PCIe-8560 and PXI-8565 expansion kits launched by ADLINK utilize the high-speed differential signal of PCI Express to achieve a remote connection of up to 7 meters between the host and PXI chassis, while maintaining complete hardware and software transparency. This article will provide engineers with a complete practical guide from the aspects of system architecture, installation configuration, signal integrity tuning, critical jumper settings, power on timing, and common compatibility issues, to help them efficiently deploy this expansion solution and quickly locate faults.

System architecture and transparency advantages

PCIe-8560 (host PCIe card) and PXI-8565 (PXI chassis system slot controller) are connected through shielded twisted pair cables to form a point-to-point PCIe x1 link, with an effective signal rate of 2.5 Gbps (per direction). The PXI-8565 has a built-in PCIe to PCI bridge that converts PCIe protocol to a standard 32-bit/33MHz PCI bus, driving all peripheral modules on the PXI backplane. Due to the complete transparency of the entire bridging process to the operating system and drivers, the PXI module is recognized as being directly plugged into the host's internal PCI slot, without the need to install any additional software or drivers, greatly reducing deployment complexity.

The typical application scenarios of this kit include:

Semiconductor testing sorting machine: Keep the PXI instrument away from the high-temperature area of the production line and place the host at the operator's workstation.

Vehicle or onboard testing: The host is located in the control room, and the PXI chassis is close to the sensors to reduce the attenuation of long line analog signals.

High density digital I/O system: Utilizing PXI chassis multi slot expansion, the host only needs one PCIe slot.

Hardware installation steps and key precautions

1. Installation of PCIe-8560 on the host side

Turn off the host power, select any x1, x4, x8, or x16 PCIe slot, and insert the PCIe-8560 (low profile size 68.9mm × 86.65mm, power consumption only) 3.3V@210mA ）.

Attention: This card is an x1 gold finger and can be installed in any PCIe slot without external power supply.

2. Installation of PXI-8565 on the PXI chassis end

It must be installed in the system slot, not the peripheral slot. Taking ADLINK PXIS-2508 as an example, the system slot is usually located on the leftmost side or in a specific identification position.

Before installation, ensure that the chassis is grounded, wear an anti-static wrist strap, and secure the panel screws to ensure good grounding and mechanical stability.

3. Expand cable connections

The standard packaging provides 3-meter shielded wire (ACL-EXPRESS-3), as well as 1-meter and 7-meter options. When connecting, tighten the screws at both ends to ensure good grounding of the shielding layer.

It is strictly prohibited to plug or unplug cables when the system is powered on, otherwise it may cause the host blue screen or PXI chassis to lose control, and even damage hardware.

Power on timing - key and often overlooked details

Since PCIe-8560 is essentially a PCIe to PCI bridge, during the host POST (power on self-test) phase, the BIOS scans the PCI bus and allocates resources (I/O, memory, etc.) IRQ）。 To enable the BIOS to correctly recognize all modules in the remote PXI chassis, the following sequence must be strictly followed:

First, turn on the PXI chassis power (while the host is still turned off).

Wait for a few seconds until the PXI backplane stabilizes power supply.

Turn on the host power again.

Reason: When enumerating PCI devices, the host BIOS needs to detect the presence of the PXI-8565 bridge and its subordinate devices. If the chassis is not powered on and the bridge cannot respond to configuration requests, the BIOS will ignore the bus segment, causing it to be unrecognizable even if the chassis is powered on in the future. Once this situation occurs, it is necessary to power off and restart at the same time, and then power on again in the correct order.

The shutdown sequence is the opposite:

First, shut down the host operating system and power off.

Turn off the PXI chassis power again.

If this order is violated (shut down the PXI chassis first), the host PCI bridge will detect bus hot unplugging, which may cause system crashes or data loss.

Signal integrity optimization - S1/S2 equalizer adjustment

In long-distance (especially 7-meter) transmission, high-frequency signals will be attenuated due to cable losses, while inter symbol interference (ISI) will occur. The PCIe-8560 board is equipped with a programmable signal equalizer, output swing, and de emphasis adjustment circuit, which are tuned through two sets of 4-bit DIP switches (S1 for the transmit channel and S2 for the receive channel). All adjustments must be applied simultaneously to S1 and S2 to ensure bidirectional link symmetry.

Equalizer level (Pin 1&Pin 2 combination)

Default (strongest balance): Both switches 1 and 2 are set to ON, suitable for 7-meter long lines, compensating for high-frequency losses.

Moderate balance: Only one of switches 1 or 2 is turned on (specific combinations need to refer to Table 3-2 in the manual, which lists three levels but does not clearly distinguish between each gear. In reality, the factory default is the strongest).

Weak or no equilibrium: Suitable for extremely short lines (1 meter) or situations with excellent signal quality, excessive equilibrium can amplify noise.

Output swing control (Pin 3)

Default high swing can improve signal-to-noise ratio, but may increase radiation; If the laboratory environment is sensitive to EMI, it can be changed to normal swing (switch 3 OFF).

Intensify control (Pin 4)

Default high attenuation can help compensate for high-frequency attenuation of cables; For short distances, it can be reduced to increase weight.

Optimization suggestion: If the system experiences link instability (such as random device loss or blue screen), try starting from the default strongest balance and gradually reducing it. Usually, 7 meters can be used as the strongest, 3 meters can be used as moderate, and 1 meter can be used as weak or closed. After adjustment, it is necessary to power on again for the settings to take effect.

PXI-8565 Jumper - Spread Spectrum Clock Control

The J1 jumper on PXI-8565 is used to enable or disable PCI clock spread spectrum, which is enabled by default (with three jumper caps located at positions 2-3). Spread spectrum modulation of PCI clock (33MHz) at low frequencies can significantly reduce system electromagnetic interference (EMI) and facilitate FCC/CE certification. However, in some high-precision measurement applications, spread spectrum may introduce clock jitter, which affects the accuracy of synchronous acquisition. If periodic errors are found in data collection, spread spectrum can be disabled (jumper cap moved to position 1-2), while ensuring sufficient electromagnetic shielding of the chassis.

Meaning of LED status indicator light

Both PCIe-8560 and PXI-8565 panels have D1 LED (serial link status).

The constant LED indicates that the link has been established (must meet the following conditions: cable connection is intact, PXI chassis is powered on, and host POST is in progress).

If the LED does not light up, check whether the cable is locked and whether the power supply at both ends is normal. If the LED turns off after the host is started, it may indicate that the link training has failed and the balance setting needs to be adjusted.

Common compatibility issues and systematic troubleshooting

As the kit serves as a transparent PCIe to PCI bridge, its compatibility depends on the host BIOS's ability to handle multiple PCI bus segments. The FAQ section focuses on answering the most common questions that engineers encounter:

Q1: What is the maximum extension distance?

A: 7 meters. ADLINK offers three types of cables: 1-meter, 3-meter, and 7-meter.

Q2: Do you need additional drivers?

A: No need at all, the operating system supports it natively.

Q3: How many expansion cases can a host connect to?

A: PCIe is a point-to-point topology, where one PCIe slot can only accommodate one expansion chassis. But if the host has multiple PCIe slots, multiple PCIe-8560 can be installed, each controlling a PXI chassis. In theory, the PCI bus can support 255 bus segments, but is limited by BIOS and operating system.

Q4: Why does the BIOS not recognize some modules inside the PXI chassis?

A: This is the most common question. The fundamental reason is that the BIOS resource allocation algorithm cannot handle complex bridging levels, especially when the host itself has multiple PCI devices. The solutions are as follows (in priority):

Update the host BIOS to the latest version (especially Intel 945, 965 or motherboard with updated chipset).

Disable unnecessary onboard devices (such as serial ports, parallel ports, onboard audio, secondary network cards, etc.) in BIOS settings to free up I/O and memory resources.

Remove all unnecessary PCI/PCIe cards inside the host, leaving only the graphics card and PCIe-8560 to reduce resource competition.

Attempt to insert PCIe-8560 into different PCIe slots, some slots may be directly connected to the CPU, while others are bridged through a chipset with different resource allocation strategies.

Step by step insertion test: First, insert only one module into the PXI chassis, confirm identification, and then add them one by one to determine which module is causing resource overflow.

If the above methods are ineffective, it may be necessary to contact the motherboard manufacturer for support or replace it with a server grade motherboard (usually supporting more bus segments).

Q5: Blue screen or module data error during system operation?

A: Check if the cable connections are loose, if the equalizer settings are appropriate, and if the PXI chassis power supply is sufficient (pay attention to the backplane power supply for high-power modules). In addition, confirm whether the spread spectrum clock setting of PXI-8565 conflicts with the measurement requirements.

Practical application scenarios and selection suggestions

Scenario 1: Mobile Test Vehicle

The vehicle vibrates greatly during operation, and the main unit and PXI chassis need to be placed separately. Use a 7-meter cable to secure the host to the shock absorber platform, and place the PXI chassis near the sensor side to avoid introducing noise through long analog signal lines.

Scenario 2: Aging Test Chamber

Place the PXI chassis outside the high-temperature box, connect internal sensors and switch modules through cables, and remotely monitor the host in the office to avoid personnel exposure to high-temperature environments.

Selection tip: If only a small number of PCI slots are needed, PCES-8581-4S (4-channel expansion) can be used in conjunction with PCIe-8560; If the star triggering function of PXI module synchronization triggering is required, PXI-8565 (supporting PXI backplane triggering bus) must be used.

Maintenance and Precautions

The bending radius of the cable shall not be less than the specified value (about 5cm), excessive bending may damage the internal shielding layer.

Regularly inspect the metal contacts of cable connectors and clean the oxide layer with anhydrous alcohol.

The ambient temperature should be controlled between 0~50 ℃, and the humidity should be 10%~90% without condensation.